Pull clk updates from Stephen Boyd:
"This contains no changes to the core framework. It is a collection of
various clk driver updates.
The biggest driver updates in terms of lines of code is the Allwinner
driver, closely followed by the Qualcomm and Mediatek drivers. All of
those hit high because we add so many lines of clk data. Coming in
fourth place is i.MX which also adds a bunch of clk data. This
accounts for the new driver additions this time around.
Otherwise the patches are lots of little cleanups and fixes for
various clk drivers that have baked in linux-next for a while. I
suppose one highlight or theme is that more clk drivers are being
updated to work as modules, which is interesting to see such critical
SoC infrastructure work as a loadable module.
New Drivers:
- Support qcom SM8150/SM8250 video and display clks
- Support Mediatek MT8167 clks
- Add clock for CRC block found on vf610 SoCs
- Add support for the Renesas R-Car V3U (R8A779A0) SoC
- Add support for the VSP for Resizing clock on Renesas RZ/G1H
- Support Allwinner A100 SoC clks
Removed Drivers:
- Remove i.MX21 clock driver, as i.MX21 platform support is being
dropped
Updates:
- Change how qcom's display port clks work
- Small non-critical fixes for TI clk driver
- Remove various unused variables in clk drivers
- Allow Rockchip clk driver to be a module
- Remove most __clk_lookup() calls in Samsung drivers (yay!)
- Support building i.MX ARMv8 platforms clock driver as module
- Some kerneldoc fixes here and there
- A couple of minor i.MX clk data corrections
- Update audio clock inverter and fdiv2 flag on Amlogic g12
- Make amlogic clk drivers configurable in Kconfig
- Fix Renesas VSP clock names to match corrected hardware
documentation
- Sigma-delta modulation on Allwinner R40
- Various fixes for at91 clk driver
- Use semicolons instead of commas in some places
- Mark some variables const so they can move to RO memory"
* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (102 commits)
clk: imx8mq: Fix usdhc parents order
clk: qcom: gdsc: Keep RETAIN_FF bit set if gdsc is already on
clk: Restrict CLK_HSDK to ARC_SOC_HSDK
clk: at91: sam9x60: support only two programmable clocks
clk: ingenic: Respect CLK_SET_RATE_PARENT in .round_rate
clk: ingenic: Don't tag custom clocks with CLK_SET_RATE_PARENT
clk: ingenic: Don't use CLK_SET_RATE_GATE for PLL
clk: ingenic: Use readl_poll_timeout instead of custom loop
clk: ingenic: Use to_clk_info() macro for all clocks
clk: bcm2835: add missing release if devm_clk_hw_register fails
clk: at91: clk-sam9x60-pll: remove unused variable
clk: at91: clk-main: update key before writing AT91_CKGR_MOR
clk: at91: remove the checking of parent_name
clk: clk-prima2: fix return value check in prima2_clk_init()
clk: mmp2: Fix the display clock divider base
clk: pxa: Constify static struct clk_ops
clk: baikal-t1: Mark Ethernet PLL as critical
clk: qoriq: modify MAX_PLL_DIV to 32
clk: axi-clkgen: Set power bits for fractional mode
clk: axi-clkgen: Add support for fractional dividers
...
- Support qcom SM8150/SM8250 video and display clks
- Change how qcom's display port clks work
* clk-ingenic:
clk: ingenic: Respect CLK_SET_RATE_PARENT in .round_rate
clk: ingenic: Don't tag custom clocks with CLK_SET_RATE_PARENT
clk: ingenic: Don't use CLK_SET_RATE_GATE for PLL
clk: ingenic: Use readl_poll_timeout instead of custom loop
clk: ingenic: Use to_clk_info() macro for all clocks
* clk-at91:
clk: at91: sam9x60: support only two programmable clocks
clk: at91: clk-sam9x60-pll: remove unused variable
clk: at91: clk-main: update key before writing AT91_CKGR_MOR
clk: at91: remove the checking of parent_name
* clk-kconfig:
clk: Restrict CLK_HSDK to ARC_SOC_HSDK
* clk-imx:
clk: imx8mq: Fix usdhc parents order
clk: imx: imx21: Remove clock driver
clk: imx: gate2: Fix a few typos
clk: imx: Fix and update kerneldoc
clk: imx: fix i.MX7D peripheral clk mux flags
clk: imx: fix composite peripheral flags
clk: imx: Correct the memrepair clock on imx8mp
clk: imx: Correct the root clk of media ldb on imx8mp
clk: imx: vf610: Add CRC clock
clk: imx: Explicitly include bits.h
clk: imx8qxp: Support building i.MX8QXP clock driver as module
clk: imx8m: Support module build
clk: imx: Add clock configuration for ARMv7 platforms
clk: imx: Support building i.MX common clock driver as module
clk: composite: Export clk_hw_register_composite()
clk: imx6sl: Use BIT(x) to avoid shifting signed 32-bit value by 31 bits
* clk-qcom:
clk: qcom: gdsc: Keep RETAIN_FF bit set if gdsc is already on
clk: qcom: Add display clock controller driver for SM8150 and SM8250
dt-bindings: clock: add QCOM SM8150 and SM8250 display clock bindings
clk: qcom: add video clock controller driver for SM8250
clk: qcom: add video clock controller driver for SM8150
dt-bindings: clock: add SM8250 QCOM video clock bindings
dt-bindings: clock: add SM8150 QCOM video clock bindings
dt-bindings: clock: combine qcom,sdm845-videocc and qcom,sc7180-videocc
clk: qcom: gcc-msm8994: Add missing clocks, resets and GDSCs
clk/qcom: fix spelling typo
clk: qcom: gcc-sdm660: Fix wrong parent_map
clk: qcom: dispcc: Update DP clk ops for phy design
clk: qcom: gcc-msm8939: remove defined but not used variables
clk: qcom: ipq8074: make pcie0_rchng_clk_src static
* clk-prima2:
clk: clk-prima2: fix return value check in prima2_clk_init()
* clk-bcm:
clk: bcm2835: add missing release if devm_clk_hw_register fails
clk: bcm: rpi: Add register to control pixel bvb clk
In cases where we don't reference another schema, 'additionalProperties'
can be used instead. This is preferred for now as 'unevaluatedProperties'
support isn't implemented yet.
In a few cases, this means adding some missing property definitions of
which most are for SPI bus properties. 'unevaluatedProperties' is not going
to work for the SPI bus properties anyways as they are evaluated from the
parent node, not the SPI child node.
Acked-by: Mark Brown <broonie@kernel.org>
Acked-by: Krzysztof Kozlowski <krzk@kernel.org>
Acked-by: Lee Jones <lee.jones@linaro.org>
Acked-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Acked-by: Guenter Roeck <linux@roeck-us.net>
Link: https://lore.kernel.org/r/20201005183830.486085-3-robh@kernel.org
Signed-off-by: Rob Herring <robh@kernel.org>
The clock controller schemas for i.MX 8M Mini, 8M Nano, 8M Plus and 8M
Quad are basically the same. The only minor difference appears on 8M
Quad which needs one more clock.
There is no point to have four schemas for almost the same binding. Any
fixes or changes would have to be duplicated four times.
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: Rob Herring <robh@kernel.org>
The i.MX 8 DTSes use two compatibles so update the binding to fix
dtbs_check warnings like:
arch/arm64/boot/dts/freescale/imx8mn-evk.dt.yaml: mmc@30b40000:
compatible: ['fsl,imx8mn-usdhc', 'fsl,imx7d-usdhc'] is too long
From schema: Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.yaml
arch/arm64/boot/dts/freescale/imx8mn-evk.dt.yaml: mmc@30b40000:
compatible: Additional items are not allowed ('fsl,imx7d-usdhc' was unexpected)
arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dt.yaml: mmc@30b40000:
compatible: ['fsl,imx8mn-usdhc', 'fsl,imx7d-usdhc'] is too long
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Link: https://lore.kernel.org/r/20200829062505.4642-1-krzk@kernel.org
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Update the i.MX23 clock example to align with MXS AUART binding doc to
avoid below build error:
Documentation/devicetree/bindings/clock/imx23-clock.example.dt.yaml:
serial@8006c000: clocks: [[4294967295, 32]] is too short
Documentation/devicetree/bindings/clock/imx23-clock.example.dt.yaml:
serial@8006c000: 'dmas' is a required property
Documentation/devicetree/bindings/clock/imx23-clock.example.dt.yaml:
serial@8006c000: 'dma-names' is a required property
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Link: https://lore.kernel.org/r/1597721685-9280-2-git-send-email-Anson.Huang@nxp.com
Signed-off-by: Rob Herring <robh@kernel.org>
Update the i.MX28 clock example to align with MXS AUART binding doc to
avoid below build error:
Documentation/devicetree/bindings/clock/imx28-clock.example.dt.yaml:
serial@8006a000: clocks: [[4294967295, 45]] is too short
Documentation/devicetree/bindings/clock/imx28-clock.example.dt.yaml:
serial@8006a000: compatible: Additional items are not allowed
('fsl,imx23-auart' was unexpected)
Documentation/devicetree/bindings/clock/imx28-clock.example.dt.yaml:
serial@8006a000: compatible: ['fsl,imx28-auart', 'fsl,imx23-auart']
is too long
Documentation/devicetree/bindings/clock/imx28-clock.example.dt.yaml:
serial@8006a000: 'dmas' is a required property
Documentation/devicetree/bindings/clock/imx28-clock.example.dt.yaml:
serial@8006a000: 'dma-names' is a required property
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Link: https://lore.kernel.org/r/1597721685-9280-1-git-send-email-Anson.Huang@nxp.com
Signed-off-by: Rob Herring <robh@kernel.org>
Pull more clk updates from Stephen Boyd:
"Here's some more updates that missed the last pull request because I
happened to tag the tree at an earlier point in the history of
clk-next. I must have fat fingered it and checked out an older version
of clk-next on this second computer I'm using.
This time it actually includes more code for Qualcomm SoCs, the AT91
major updates, and some Rockchip SoC clk driver updates as well. I've
corrected this flow so this shouldn't happen again"
* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (83 commits)
clk: bcm2835: Do not use prediv with bcm2711's PLLs
clk: drop unused function __clk_get_flags
clk: hsdk: Fix bad dependency on IOMEM
dt-bindings: clock: Fix YAML schemas for LPASS clocks on SC7180
clk: mmp: avoid missing prototype warning
clk: sparx5: Add Sparx5 SoC DPLL clock driver
dt-bindings: clock: sparx5: Add bindings include file
clk: qoriq: add LS1021A core pll mux options
clk: clk-atlas6: fix return value check in atlas6_clk_init()
clk: tegra: pll: Improve PLLM enable-state detection
clk: X1000: Add support for calculat REFCLK of USB PHY.
clk: JZ4780: Reformat the code to align it.
clk: JZ4780: Add functions for enable and disable USB PHY.
clk: Ingenic: Add RTC related clocks for Ingenic SoCs.
dt-bindings: clock: Add tabs to align code.
dt-bindings: clock: Add RTC related clocks for Ingenic SoCs.
clk: davinci: Use fallthrough pseudo-keyword
clk: imx: Use fallthrough pseudo-keyword
clk: qcom: gcc-sdm660: Fix up gcc_mss_mnoc_bimc_axi_clk
clk: qcom: gcc-sdm660: Add missing modem reset
...
Pull clk updates from Stephen Boyd:
"It looks like a smaller batch of clk updates this time around.
In the core framework we just have some minor tweaks and a debugfs
feature, so not much to see there. The driver updates are fairly well
split between AT91 and Qualcomm clk support. Adding those two drivers
together equals about 50% of the diffstat.
Otherwise, the big amount of work this time was on supporting
Broadcom's Raspberry Pi firmware clks.
Highlights:
Core:
- Document clk_hw_round_rate() so it gets some more use
- Remove unused __clk_get_flags()
- Add a prepare/enable debugfs feature similar to rate setting
New Drivers:
- Add support for SAMA7G5 SoC clks
- Enable CPU clks on Qualcomm IPQ6018 SoCs
- Enable CPU clks on Qualcomm MSM8996 SoCs
- GPU clk support for Qualcomm SM8150 and SM8250 SoCs
- Audio clks on Qualcomm SC7180 SoCs
- Microchip Sparx5 DPLL clk
- Add support for the new Renesas RZ/G2H (R8A774E1) SoC
Updates:
- Make defines for bcm63xx-gate clks to use in DT
- Support BCM2711 SoC firmware clks
- Add HDMI clks for BCM2711 SoCs
- Add RTC related clks on Ingenic SoCs
- Support USB PHY clks on Ingenic SoCs
- Support gate clks on BCM6318 SoCs
- RMU and DMAC/GPIO clock support for Actions Semi S500 SoCs
- Use poll_timeout functions in Rockchip clk driver
- Support Rockchip rk3288w SoC variant
- Mark mac_lbtest critical on Rockchip rk3188
- Add CAAM clock support for i.MX vf610 driver
- Add MU root clock support for i.MX imx8mp driver
- Amlogic g12: add neural network accelerator clock sources
- Amlogic meson8: remove critical flag for main PLL divider
- Amlogic meson8: add video decoder clock gates
- Convert one more Renesas DT binding to json-schema
- Enhance critical clock handling on Renesas platforms to only
consider clocks that were enabled at boot time"
* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (79 commits)
clk: qcom: gcc: Make disp gpll0 branch aon for sc7180/sdm845
ipq806x: gcc: add support for child probe
clk: qcom: msm8996: Make symbol 'cpu_msm8996_clks' static
clk: qcom: ipq8074: Add correct index for PCIe clocks
clk: <linux/clk-provider.h>: drop a duplicated word
clk: renesas: cpg-mssr: Add r8a774e1 support
dt-bindings: clock: renesas,cpg-mssr: Document r8a774e1
clk: Drop duplicate selection in Kconfig
clk: qcom: smd: Add support for MSM8992/4 rpm clocks
clk: qcom: ipq8074: Add missing clocks for pcie
dt-bindings: clock: qcom: ipq8074: Add missing bindings for PCIe
Replace HTTP links with HTTPS ones: Common CLK framework
clk: qcom: Add CPU clock driver for msm8996
dt-bindings: clk: qcom: Add bindings for CPU clock for msm8996
soc: qcom: Separate kryo l2 accessors from PMU driver
clk: meson: meson8b: add the vclk2_en gate clock
clk: meson: meson8b: add the vclk_en gate clock
clk: qcom: Fix return value check in apss_ipq6018_probe()
clk: bcm: dvp: Add missing module informations
clk: meson: meson8b: Drop CLK_IS_CRITICAL from fclk_div2
...
Pull Devicetree updates from Rob Herring:
- Improve device links cycle detection and breaking. Add more bindings
for device link dependencies.
- Refactor parsing 'no-map' in __reserved_mem_alloc_size()
- Improve DT unittest 'ranges' and 'dma-ranges' test case to check
differing cell sizes
- Various http to https link conversions
- Add a schema check to prevent 'syscon' from being used by itself
without a more specific compatible
- A bunch more DT binding conversions to schema
* tag 'devicetree-for-5.9' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux: (55 commits)
of: reserved-memory: remove duplicated call to of_get_flat_dt_prop() for no-map node
of: unittest: Use bigger address cells to catch parser regressions
dt-bindings: memory-controllers: Convert mmdc to json-schema
dt-bindings: mtd: Convert imx nand to json-schema
dt-bindings: mtd: Convert gpmi nand to json-schema
dt-bindings: iio: io-channel-mux: Fix compatible string in example code
of: property: Add device link support for pinctrl-0 through pinctrl-8
of: property: Add device link support for multiple DT bindings
dt-bindings: phy: ti: phy-gmii-sel: convert bindings to json-schema
dt-bindings: mux: mux.h: drop a duplicated word
dt-bindings: misc: Convert olpc,xo1.75-ec to json-schema
dt-bindings: aspeed-lpc: Replace HTTP links with HTTPS ones
dt-bindings: drm/bridge: Replace HTTP links with HTTPS ones
drm/tilcdc: Replace HTTP links with HTTPS ones
dt-bindings: iommu: renesas,ipmmu-vmsa: Add r8a774e1 support
dt-bindings: fpga: Replace HTTP links with HTTPS ones
dt-bindings: virtio: Replace HTTP links with HTTPS ones
dt-bindings: media: imx274: Add optional input clock and supplies
dt-bindings: i2c-gpio: Use 'deprecated' keyword on deprecated properties
dt-bindings: interrupt-controller: Fix typos in loongson,liointc.yaml
...
Pull new ARM SoC support from Arnd Bergmann:
"There are three SoC families newly dded to the 32-bit and 64-bit Arm
architecture code in the kernel this time:
- Daniel Palmer adds initial support for two chips made by MStar, a
taiwanese SoC manufacturer that became part of Mediatek in 2012.
For now, the added support is fairly minimal, with just two of its
Cortex-A7 based 32-bit camera chips getting support for a limited
set of on-chip peripherals.
- Lars Povlsen from Microchip adds support for their new Sparx5
family of ethernet switch chips using 64-bit Cortex-A53 cores.
These are descended from earlier VSC7xxx SparX and Ocelot chips
using 32-bit MIPS cores.
- Daniele Alessandrelli from Intel adds support for the new Keem Bay
SoC for computer vision, built around a Movidius VPU with Linux
running on Arm Cortex-A53 cores"
* tag 'arm-newsoc-5.9' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (38 commits)
ARM: mstar: Correct the compatible string for pmsleep
dt-bindings: arm: mstar: remove the binding description for mstar,pmsleep
dt-bindings: mfd: syscon: add compatible string for mstar,msc313-pmsleep
ARM: mstar: Add reboot support
ARM: mstar: Add "pmsleep" node to base dtsi
ARM: mstar: Add PMU
ARM: mstar: Adjust IMI size for infinity3
ARM: mstar: Adjust IMI size for mercury5
ARM: mstar: Adjust IMI size of infinity
ARM: mstar: Add IMI SRAM region
dt-bindings: arm: mstar: Move existing MStar binding descriptions
dt-bindings: arm: mstar: Add binding details for mstar, pmsleep
ARM: mstar: Fix dts filename for 70mai midrive d08
ARM: mstar: Add dts for 70mai midrive d08
ARM: mstar: Add dts for msc313(e) based BreadBee boards
ARM: mstar: Add mercury5 series dtsis
ARM: mstar: Add infinity/infinity3 family dtsis
ARM: mstar: Add Armv7 base dtsi
ARM: mstar: Add binding details for mstar,l3bridge
ARM: mstar: Add machine for MStar/Sigmastar Armv7 SoCs
...
- Enable CPU clks on Qualcomm IPQ6018 SoCs
- Enable CPU clks on Qualcomm MSM8996 SoCs
- GPU clk support for Qualcomm SM8150 and SM8250 SoCs
- Audio clks on Qualcomm SC7180 SoCs
- Make defines for bcm63xx-gate clks to use in DT
- Support gate clks on BCM6318 SoCs
- Add HDMI clks for BCM2711 SoCs
- Support BCM2711 SoC firmware clks
* clk-socfpga:
clk: socfpga: agilex: mpu_l2ram_clk should be mpu_ccu_clk
clk: socfpga: agilex: add nand_x_clk and nand_ecc_clk
dt-bindings: agilex: add NAND_X_CLK and NAND_ECC_CLK
* clk-doc:
clk: Clean up kernel-doc errors
clk: <linux/clk-provider.h>: drop a duplicated word
clk: add function documentation for clk_hw_round_rate()
* clk-qcom: (38 commits)
dt-bindings: clock: Fix YAML schemas for LPASS clocks on SC7180
clk: qcom: gcc-sdm660: Fix up gcc_mss_mnoc_bimc_axi_clk
clk: qcom: gcc-sdm660: Add missing modem reset
clk: qcom: lpass: Add support for LPASS clock controller for SC7180
clk: qcom: gcc: Add support for GCC LPASS clock for SC7180
dt-bindings: clock: Add YAML schemas for LPASS clocks on SC7180
clk: qcom: gdsc: Add support to enable retention of GSDCR
clk: qcom: Export gdsc_gx_do_nothing_enable() to modules
clk: qcom: Add graphics clock controller driver for SM8250
clk: qcom: Add graphics clock controller driver for SM8150
clk: qcom: add common gdsc_gx_do_nothing_enable for gpucc drivers
dt-bindings: clock: add SM8250 QCOM Graphics clock bindings
dt-bindings: clock: add SM8150 QCOM Graphics clock bindings
dt-bindings: clock: combine qcom,sdm845-gpucc and qcom,sc7180-gpucc
clk: qcom: gcc: remove unnecessary vco_table from SM8150
clk: qcom: clk-alpha-pll: use the right PCAL_DONE value for lucid pll
clk: qcom: clk-alpha-pll: same regs and ops for trion and lucid
clk: qcom: clk-alpha-pll: remove unused/incorrect PLL_CAL_VAL
clk: qcom: gcc: fix sm8150 GPU and NPU clocks
dt-bindings: clock: Fix qcom,msm8996-apcc yaml syntax
...
* clk-vc5:
clk: vc5: use a dedicated struct to describe the output drivers
dt-bindings: clk: versaclock5: convert to yaml
MAINTAINERS: take over IDT VersaClock 5 clock driver
dt-bindings: clk: versaclock5: fix 'idt' prefix typos
clk: vc5: Add memory check to prevent oops
clk: vc5: fix use of memory after it has been kfree'd
clk: vc5: Enable addition output configurations of the Versaclock
dt: Add additional option bindings for IDT VersaClock
clk: vc5: Allow Versaclock driver to support multiple instances
* clk-bcm: (44 commits)
clk: bcm2835: Do not use prediv with bcm2711's PLLs
dt-bindings: arm: bcm: Add a select to the RPI Firmware binding
clk: bcm: dvp: Add missing module informations
clk: bcm: rpi: Remove the quirks for the CPU clock
clk: bcm2835: Don't cache the PLLB rate
clk: bcm2835: Allow custom CCF flags for the PLLs
Revert "clk: bcm2835: remove pllb"
clk: bcm: rpi: Give firmware clocks a name
clk: bcm: rpi: Discover the firmware clocks
clk: bcm: rpi: Add an enum for the firmware clocks
clk: bcm: rpi: Add DT provider for the clocks
clk: bcm: rpi: Make the PLLB registration function return a clk_hw
clk: bcm: rpi: Split pllb clock hooks
clk: bcm: rpi: Rename is_prepared function
clk: bcm: rpi: Pass the clocks data to the firmware function
clk: bcm: rpi: Add clock id to data
clk: bcm: rpi: Create a data structure for the clocks
clk: bcm: rpi: Use CCF boundaries instead of rolling our own
clk: bcm: rpi: Make sure the clkdev lookup is removed
clk: bcm: rpi: Switch to clk_hw_register_clkdev
...
The YAML schemas that landed forgot one clock: "bi_tcxo". Presumably
the bindings were developed against the v4 version of the driver and
when the ".name" was removed in v5 of the driver things broke.
While touching this, add the needed includes in each example. I
believe both examples are supposed to be independent of each other.
Let's fix the bindings.
Fixes: 381cc6f97c ("dt-bindings: clock: Add YAML schemas for LPASS clocks on SC7180")
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Link: https://lore.kernel.org/r/20200731133006.1.Iee81b115f5be50d6d69500fe1bda11bba6e16143@changeid
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* clk-renesas:
clk: renesas: rzg2: Mark RWDT clocks as critical
clk: renesas: rcar-gen3: Mark RWDT clocks as critical
clk: renesas: cpg-mssr: Mark clocks as critical only if on at boot
dt-bindings: clock: renesas: cpg: Convert to json-schema
Rationale:
Reduces attack surface on kernel devs opening the links for MITM
as HTTPS traffic is much harder to manipulate.
Deterministic algorithm:
For each file:
If not .svg:
For each line:
If doesn't contain `\bxmlns\b`:
For each link, `\bhttp://[^# \t\r\n]*(?:\w|/)`:
If both the HTTP and HTTPS versions
return 200 OK and serve the same content:
Replace HTTP with HTTPS.
Signed-off-by: Alexander A. Klimov <grandmaster@al2klimov.de>
Link: https://lore.kernel.org/r/20200703175114.15027-1-grandmaster@al2klimov.de
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
- Enable CPU clks on Qualcomm MSM8996 SoCs
* clk-qcom:
clk: qcom: Add CPU clock driver for msm8996
dt-bindings: clk: qcom: Add bindings for CPU clock for msm8996
soc: qcom: Separate kryo l2 accessors from PMU driver
clk: qcom: Fix return value check in apss_ipq6018_probe()
Each of the CPU clusters (Power and Perf) on msm8996 are
clocked via 2 PLLs, a primary and alternate. There are also
2 Mux'es, a primary and secondary all connected together
as shown below
+-------+
XO | |
+------------------>0 |
| |
PLL/2 | SMUX +----+
+------->1 | |
| | | |
| +-------+ | +-------+
| +---->0 |
| | |
+---------------+ | +----------->1 | CPU clk
|Primary PLL +----+ PLL_EARLY | | +------>
| +------+-----------+ +------>2 PMUX |
+---------------+ | | | |
| +------+ | +-->3 |
+--^+ ACD +-----+ | +-------+
+---------------+ +------+ |
|Alt PLL | |
| +---------------------------+
+---------------+ PLL_EARLY
The primary PLL is what drives the CPU clk, except for times
when we are reprogramming the PLL itself (for rate changes) when
we temporarily switch to an alternate PLL. A subsequent patch adds
support to switch between primary and alternate PLL during rate
changes.
The primary PLL operates on a single VCO range, between 600MHz
and 3GHz. However the CPUs do support OPPs with frequencies
between 300MHz and 600MHz. In order to support running the CPUs
at those frequencies we end up having to lock the PLL at twice
the rate and drive the CPU clk via the PLL/2 output and SMUX.
Signed-off-by: Ilia Lin <ilialin@codeaurora.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/1593766185-16346-4-git-send-email-loic.poulain@linaro.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Devicetree fixes for v5.8, take 2:
- Sync dtc to upstream to pick up fixes for I2C bus checks and quiet
warnings
- Various fixes for DT binding check warnings
- A couple of build fixes/improvements for binding checks
- ReST formatting improvements for writing-schema.rst
- Document reference fixes
In i.MX8QXP LPCG binding's example, "fsl,imx7d-usdhc" as fallback
compatible is incorrect, remove it to avoid below build error:
Documentation/devicetree/bindings/clock/imx8qxp-lpcg.example.dt.yaml:
mmc@5b010000: compatible: Additional items are not allowed ('fsl,imx7d-usdhc' was unexpected)
Documentation/devicetree/bindings/clock/imx8qxp-lpcg.example.dt.yaml:
mmc@5b010000: compatible: ['fsl,imx8qxp-usdhc', 'fsl,imx7d-usdhc'] is too long
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Link: https://lore.kernel.org/r/1592450578-30140-3-git-send-email-Anson.Huang@nxp.com
Signed-off-by: Rob Herring <robh@kernel.org>
