Pull SoC DT updates from Arnd Bergmann:
"There are a couple new SoCs that are supported for the first time:
- AMD Pensando Elba is a data processing unit based on Cortex-A72 CPU
cores
- Sophgo makes RISC-V based chips, and we now support the CV1800B
chip used in the milkv-duo board and the massive sg2042 chip in the
milkv-pioneer, a 64-core developer workstation.
- Qualcomm Snapdragon 720G (sm7125) is a close relative of Snapdragon
7c and gets added with some Xiaomi phones
- Renesas gains support for the R8A779F4 (R-Car S4-8) automotive SoC
and the RZ/G3S (R9A08G045) embedded SoC.
There are also a bunch of newly supported machines that use already
supported chips. On the 32-bit side, we have:
- USRobotics USR8200 is a NAS/Firewall/router based on the ancient
Intel IXP4xx platform
- A couple of machines based on the NXP i.MX5 and i.MX6 platforms
- One machine each for Allwinner V3s, Aspeed AST2600, Microchip
sama5d29 and ST STM32mp157
The other ones all use arm64 cores on chips from allwinner, amlogic,
freescale, mediatek, qualcomm and rockchip"
* tag 'soc-dt-6.7' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (641 commits)
ARM: dts: BCM5301X: Set switch ports for Linksys EA9200
ARM: dts: BCM5301X: Set fixed-link for extra Netgear R8000 CPU ports
ARM: dts: BCM5301X: Explicitly disable unused switch CPU ports
ARM: dts: BCM5301X: Relicense Vivek's code to the GPL 2.0+ / MIT
ARM: dts: BCM5301X: Relicense Felix's code to the GPL 2.0+ / MIT
ARM: dts: BCM5301X: Set MAC address for Asus RT-AC87U
arm64: dts: socionext: add missing cache properties
riscv: dts: thead: convert isa detection to new properties
arm64: dts: Update cache properties for socionext
arm64: dts: ti: k3-am654-idk: Add ICSSG Ethernet ports
arm64: dts: ti: k3-am654-icssg2: add ICSSG2 Ethernet support
arm64: dts: ti: k3-am65-main: Add ICSSG IEP nodes
arm64: dts: ti: k3-am62p5-sk: Updates for SK EVM
arm64: dts: ti: k3-am62p: Add nodes for more IPs
arm64: dts: rockchip: Add Turing RK1 SoM support
dt-bindings: arm: rockchip: Add Turing RK1
dt-bindings: vendor-prefixes: add turing
arm64: dts: rockchip: Add DFI to rk3588s
arm64: dts: rockchip: Add DFI to rk356x
arm64: dts: rockchip: Always enable DFI on rk3399
...
RISC-V Devicetrees for v6.7
StarFive:
Things are a bit slower for StarFive this window, there's only the
addition of audio related DT nodes to speak of here.
Generic:
The SiFive, StarFive and Microchip devicetrees have had my replacement
ISA extension detection properties added. Unfortunately, the old
"riscv,isa" property never defined exactly what the extensions it
contained meant, and people were want to fill it in incorrectly (and
call upstream kernel devs idiots for not doing the same). The new
properties have explicit definitions and hopefully will stand up better
to some of the variation from RVI.
Sophgo:
Two new SoCs, one is probably the first of several with up/down tuned
variants, that have a pair of T-Head c906 cores and appear aimed at the
IP camera, smart <insert whatever> etc markets. They are intended to run
in AMP mode, with an RTOS on the less powerful core. The other is far
more interesting to kernel developers however, the 64-core SG2042, with
more recent c920 cores from T-Head at 2 GHz. For both, support is at a
very basic stage - some of the same developers are working on them as
other T-Head powered SoCs, but hopefully things will move beyond a basic
console boot. The goal is for Chen Wang to take over maintaining the
Sophgo support once they have some more experience with the process.
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
* tag 'riscv-dt-for-v6.7' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux: (22 commits)
riscv: dts: starfive: convert isa detection to new properties
riscv: dts: sifive: convert isa detection to new properties
riscv: dts: microchip: convert isa detection to new properties
riscv: dts: sophgo: add Milk-V Duo board device tree
riscv: dts: sophgo: add initial CV1800B SoC device tree
dt-bindings: riscv: Add Milk-V Duo board compatibles
dt-bindings: timer: Add SOPHGO CV1800B clint
dt-bindings: interrupt-controller: Add SOPHGO CV1800B plic
riscv: defconfig: enable SOPHGO SoC
riscv: dts: sophgo: add Milk-V Pioneer board device tree
riscv: dts: add initial Sophgo SG2042 SoC device tree
dt-bindings: interrupt-controller: Add Sophgo sg2042 CLINT mswi
dt-bindings: timer: Add Sophgo sg2042 CLINT timer
dt-bindings: interrupt-controller: Add Sophgo SG2042 PLIC
dt-bindings: riscv: Add T-HEAD C920 compatibles
dt-bindings: riscv: add sophgo sg2042 bindings
dt-bindings: vendor-prefixes: add milkv/sophgo
riscv: Add SOPHGO SOC family Kconfig support
riscv: dts: starfive: add assigned-clock* to limit frquency
riscv: dts: starfive: Add JH7110 PWM-DAC support
...
Link: https://lore.kernel.org/r/20231016-filing-payroll-7aca51b8f1a3@spud
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Convert the jh7100 and jh7110 devicetrees to use the new properties
"riscv,isa-base" & "riscv,isa-extensions".
For compatibility with other projects, "riscv,isa" remains.
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Convert the fu540 and fu740 devicetrees to use the new properties
"riscv,isa-base" & "riscv,isa-extensions".
For compatibility with other projects, "riscv,isa" remains.
Reviewed-by: Samuel Holland <samuel.holland@sifive.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Convert the PolarFire SoC devicetrees to use the new properties
"riscv,isa-base" & "riscv,isa-extensions".
For compatibility with other projects, "riscv,isa" remains.
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
The ss pin of spi0 is the same as sck pin. According to the
visionfive 2 documentation, it should be pin 49 instead of 48.
Fixes: 74fb20c8f0 ("riscv: dts: starfive: Add spi node and pins configuration")
Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Signed-off-by: Nam Cao <namcao@linutronix.de>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Milk-V Duo[1] board is an embedded development platform based on the
CV1800B chip. Add minimal device tree files for the development board.
Support basic uart drivers, so supports booting to a basic shell.
Link: https://milkv.io/duo [1]
Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
Acked-by: Chen Wang <unicorn_wang@outlook.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
usb0 was disabled by mistake when merging, so enable it.
Fixes: e7c304c034 ("riscv: dts: starfive: jh7110: add the node and pins configuration for tdm")
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
The Starfive VisionFive 2 has a 16MiB NOR flash, while the reserved-data
partition is declared starting at address 0x600000 with a size of
0x1000000. This causes the kernel to output the following warning:
[ 22.156589] mtd: partition "reserved-data" extends beyond the end of device "13010000.spi.0" -- size truncated to 0xa00000
It seems to be a confusion between the size of the partition and the end
address. Fix that by specifying the right size.
Fixes: 8384087a42 ("riscv: dts: starfive: Add QSPI controller node for StarFive JH7110 SoC")
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
RISC-V Devicetrees for v6.6 Part 2
T-Head:
Add a second minimal devicetree for the second board using the th1520
SoC, the BeagleV Ahead. As with the Lichee Pi 4a, this is sufficient
only for booting to a console, with work on the mmc, clocks and ethernet
sides of things under way. A relicense to a dual licence for the
existing devicetree files is also done, for good measure.
RISC-V Devicetrees for v6.6-pt2
StarFive:
Fix the sort order of some nodes that I resolved incorrectly during a
merge conflict.
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
* tag 'riscv-dt-for-v6.6-pt2' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux:
riscv: dts: change TH1520 files to dual license
riscv: dts: thead: add BeagleV Ahead board device tree
dt-bindings: riscv: Add BeagleV Ahead board compatibles
riscv: dts: starfive: fix jh7110 qspi sort order
Link: https://lore.kernel.org/r/20230819-unwieldy-railing-9bba2b176aa7@spud
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
RISC-V Devicetrees for v6.6
StarFive:
There's only StarFive stuff this time around, starting with some
bindings to get clock ID defines out of the binding headers. Getting
these (and the syscon bindings) in unblocked a swathe of stuff sitting
on the list. Added are: new clock controllers and sycons, ethernet
support, thermal sensors, USB and PCIe PHYs, hwrng, mmc and a few more
besides for the VisionFive v2. The original VisionFive and BeagleV
Starlight got some the thermal sensor support too, as that is supported
by the same driver. These changes make the board actually usable with
something other than an initramfs.
Overlay support by way of the -@ flag set during dtb building, is added
also.
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
* tag 'riscv-dt-for-v6.6' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux: (26 commits)
riscv: dts: starfive: jh7110: Fix GMAC configuration
riscv: dts: starfive - Add hwrng node for JH7110 SoC
riscv: dts: starfive - Add crypto and DMA node for JH7110
riscv: dts: starfive: Add mmc nodes on VisionFive 2 board
riscv: dts: starfive: enable DCDC1&ALDO4 node in axp15060
riscv: dts: starfive: Add QSPI controller node for StarFive JH7110 SoC
riscv: dts: starfive: jh7110: add the node and pins configuration for tdm
riscv: dts: starfive: jh7110: add dma controller node
riscv: dts: starfive: Add spi node and pins configuration
riscv: dts: starfive: Add USB dts node for JH7110
riscv: dts: starfive: Add USB and PCIe PHY nodes for JH7110
riscv: dts: starfive: jh7110: Add temperature sensor node and thermal-zones
riscv: dts: starfive: jh7100: Add temperature sensor node and thermal-zones
riscv: dts: starfive: visionfive 2: Add configuration of gmac and phy
riscv: dts: starfive: jh7110: Add ethernet device nodes
riscv: dts: starfive: jh7110: Add PLL clocks source in SYSCRG node
riscv: dts: starfive: jh7110: Add syscon nodes
riscv: dts: starfive: jh7110: Add STGCRG/ISPCRG/VOUTCRG nodes
riscv: dts: starfive: jh7110: Add DVP and HDMI TX pixel external clocks
dt-bindings: clock: Add StarFive JH7110 Video-Output clock and reset generator
...
Link: https://lore.kernel.org/r/20230813-naturist-fragment-ac7d10c453ba@spud
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
The Allwinner D1, T113 provide two CAN controllers that are variants
of the R40 controller.
I have tested support for these controllers on two boards:
- A Lichee Panel RV 86 Panel running a D1 chip
- A Mango Pi MQ Dual running a T113-s3 chip
Both of these fully support both CAN controllers.
Signed-off-by: John Watts <contact@jookia.org>
Link: https://lore.kernel.org/r/20230807191952.2019208-1-contact@jookia.org
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
- Add D1 GPADC node
- Introduce support for OrangePi Zero 3 SBC
- Enable DT overlay support for Allwinner H3 boards
* tag 'sunxi-dt-for-6.6-1' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux:
arm: dts: Enable device-tree overlay support for sun8i-h3 pi devices
arm64: dts: allwinner: h616: Add OrangePi Zero 3 board support
dt-bindings: arm: sunxi: document Orange Pi Zero 3 board name
arm64: dts: allwinner: h616: Split Orange Pi Zero 2 DT
riscv: dts: allwinner: d1: Add GPADC node
Link: https://lore.kernel.org/r/20230806180546.GA127039@jernej-laptop
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
dtbs_check w/ W=1 complains:
Warning (unit_address_vs_reg): /soc/ethernet@11c20000/ethernet-phy@7: node has a unit name, but no reg or ranges property
Warning (avoid_unnecessary_addr_size): /soc/ethernet@11c20000: unnecessary #address-cells/#size-cells without "ranges" or child "reg" property
The ethernet@11c20000 node is guarded by an `#if (!SW_ET0_EN_N)` in
rzg2ul-smarc-som.dtsi, where the phy child node is added. In
rzfive-smarc-som.dtsi, the ethernet node is marked disabled & the
interrupt properties are deleted from the phy child node. As a result,
the produced dts looks like:
ethernet@11c20000 {
compatible = "renesas,r9a07g043-gbeth",
"renesas,rzg2l-gbeth";
/* snip */
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
ethernet-phy@7 {
};
};
Adding a corresponding `#if (!SW_ET0_EN_N)` around the node in
rzfive-smarc-som.dtsi avoids the complaint, as the empty child node is
not added:
ethernet@11c20000 {
compatible = "renesas,r9a07g043-gbeth",
"renesas,rzg2l-gbeth";
/* snip */
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20230712-squealer-walmart-9587342ddec1@wendy
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Add temperature sensor and thermal-zones support for
the StarFive JH7110 SoC. CPUFreq cooling is supported
in thermal-zones.
Co-developed-by: Emil Renner Berthing <kernel@esmil.dk>
Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
