Konrad Dybcio
2d70a9002e
drm/msm/a6xx: Fix unknown speedbin case
...
[ Upstream commit 75cb60d4f5c928a05e44c928a05e44konrad.dybcio@linaro.org >
Patchwork: https://patchwork.freedesktop.org/patch/559604/
Signed-off-by: Rob Clark <robdclark@chromium.org >
Signed-off-by: Sasha Levin <sashal@kernel.org >
2023-11-20 11:59:11 +01:00
Konrad Dybcio
34b149ecae
drm/msm/a6xx: Bail out early if setting GPU OOB fails
...
If the GMU can't guarantee the required resources are up, trying to
bring up the GPU is a lost cause. Return early if setting GPU OOB
fails.
Tested-by: Neil Armstrong <neil.armstrong@linaro.org > # on SM8550-QRD
Tested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org > # sm8450
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org >
Patchwork: https://patchwork.freedesktop.org/patch/551830/
Signed-off-by: Rob Clark <robdclark@chromium.org >
2023-08-17 10:09:54 -07:00
Konrad Dybcio
c5597e58a5
drm/msm/a6xx: Move LLC accessors to the common header
...
Move these wrappers in preparation for use in a6xx_gmu.c
Tested-by: Neil Armstrong <neil.armstrong@linaro.org > # on SM8550-QRD
Tested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org > # sm8450
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org >
Patchwork: https://patchwork.freedesktop.org/patch/551824/
Signed-off-by: Rob Clark <robdclark@chromium.org >
2023-08-17 10:09:53 -07:00
Konrad Dybcio
26ed8d3dc0
drm/msm/a6xx: Introduce a6xx_llc_read
...
Add a helper that does exactly what it says on the can, it'll be
required for A7xx.
Tested-by: Neil Armstrong <neil.armstrong@linaro.org > # on SM8550-QRD
Tested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org > # sm8450
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org >
Patchwork: https://patchwork.freedesktop.org/patch/551828/
Signed-off-by: Rob Clark <robdclark@chromium.org >
2023-08-17 10:09:53 -07:00
Rob Clark
3136a0f835
drm/msm/a6xx: Fix GMU lockdep splat
...
For normal GPU devfreq, we need to acquire the GMU lock while already
holding devfreq locks. But in the teardown path, we were calling
dev_pm_domain_detach() while already holding the GMU lock, resulting in
this lockdep splat:
======================================================
WARNING: possible circular locking dependency detected
6.4.3-debug+ #3 Not tainted
------------------------------------------------------
ring0/391 is trying to acquire lock:
ffffff80a025c078 (&devfreq->lock){+.+.}-{3:3}, at: qos_notifier_call+0x30/0x74
but task is already holding lock:
ffffff809b8c1ce8 (&(c->notifiers)->rwsem){++++}-{3:3}, at: blocking_notifier_call_chain+0x34/0x78
which lock already depends on the new lock.
the existing dependency chain (in reverse order) is:
-> #4 (&(c->notifiers)->rwsem){++++}-{3:3}:
down_write+0x58/0x74
__blocking_notifier_chain_register+0x64/0x84
blocking_notifier_chain_register+0x1c/0x28
freq_qos_add_notifier+0x5c/0x7c
dev_pm_qos_add_notifier+0xd4/0xf0
devfreq_add_device+0x42c/0x560
devm_devfreq_add_device+0x6c/0xb8
msm_devfreq_init+0xa8/0x16c [msm]
msm_gpu_init+0x368/0x54c [msm]
adreno_gpu_init+0x248/0x2b0 [msm]
a6xx_gpu_init+0x2d0/0x384 [msm]
adreno_bind+0x264/0x2bc [msm]
component_bind_all+0x124/0x1f4
msm_drm_bind+0x2d0/0x5f4 [msm]
try_to_bring_up_aggregate_device+0x88/0x1a4
__component_add+0xd4/0x128
component_add+0x1c/0x28
dp_display_probe+0x37c/0x3c0 [msm]
platform_probe+0x70/0xc0
really_probe+0x148/0x280
__driver_probe_device+0xfc/0x114
driver_probe_device+0x44/0x100
__device_attach_driver+0x64/0xdc
bus_for_each_drv+0xb0/0xd8
__device_attach+0xe4/0x140
device_initial_probe+0x1c/0x28
bus_probe_device+0x44/0xb0
deferred_probe_work_func+0xb0/0xc8
process_one_work+0x288/0x3d8
worker_thread+0x1f0/0x260
kthread+0xf0/0x100
ret_from_fork+0x10/0x20
-> #3 (dev_pm_qos_mtx){+.+.}-{3:3}:
__mutex_lock+0xc8/0x388
mutex_lock_nested+0x2c/0x38
dev_pm_qos_remove_notifier+0x3c/0xc8
genpd_remove_device+0x40/0x11c
genpd_dev_pm_detach+0x88/0x130
dev_pm_domain_detach+0x2c/0x3c
a6xx_gmu_remove+0x44/0xdc [msm]
a6xx_destroy+0x7c/0xa4 [msm]
adreno_unbind+0x50/0x64 [msm]
component_unbind+0x44/0x64
component_unbind_all+0xb4/0xbc
msm_drm_uninit.isra.0+0x124/0x17c [msm]
msm_drm_bind+0x340/0x5f4 [msm]
try_to_bring_up_aggregate_device+0x88/0x1a4
__component_add+0xd4/0x128
component_add+0x1c/0x28
dp_display_probe+0x37c/0x3c0 [msm]
platform_probe+0x70/0xc0
really_probe+0x148/0x280
__driver_probe_device+0xfc/0x114
driver_probe_device+0x44/0x100
__device_attach_driver+0x64/0xdc
bus_for_each_drv+0xb0/0xd8
__device_attach+0xe4/0x140
device_initial_probe+0x1c/0x28
bus_probe_device+0x44/0xb0
deferred_probe_work_func+0xb0/0xc8
process_one_work+0x288/0x3d8
worker_thread+0x1f0/0x260
kthread+0xf0/0x100
ret_from_fork+0x10/0x20
-> #2 (&a6xx_gpu->gmu.lock){+.+.}-{3:3}:
__mutex_lock+0xc8/0x388
mutex_lock_nested+0x2c/0x38
a6xx_gpu_set_freq+0x38/0x64 [msm]
msm_devfreq_target+0x170/0x18c [msm]
devfreq_set_target+0x90/0x1e4
devfreq_update_target+0xb4/0xf0
update_devfreq+0x1c/0x28
devfreq_monitor+0x3c/0x10c
process_one_work+0x288/0x3d8
worker_thread+0x1f0/0x260
kthread+0xf0/0x100
ret_from_fork+0x10/0x20
-> #1 (&df->lock){+.+.}-{3:3}:
__mutex_lock+0xc8/0x388
mutex_lock_nested+0x2c/0x38
msm_devfreq_get_dev_status+0x4c/0x104 [msm]
devfreq_simple_ondemand_func+0x5c/0x128
devfreq_update_target+0x68/0xf0
update_devfreq+0x1c/0x28
devfreq_monitor+0x3c/0x10c
process_one_work+0x288/0x3d8
worker_thread+0x1f0/0x260
kthread+0xf0/0x100
ret_from_fork+0x10/0x20
-> #0 (&devfreq->lock){+.+.}-{3:3}:
__lock_acquire+0xdf8/0x109c
lock_acquire+0x234/0x284
__mutex_lock+0xc8/0x388
mutex_lock_nested+0x2c/0x38
qos_notifier_call+0x30/0x74
qos_min_notifier_call+0x1c/0x28
notifier_call_chain+0xf4/0x114
blocking_notifier_call_chain+0x4c/0x78
pm_qos_update_target+0x184/0x190
freq_qos_apply+0x4c/0x64
apply_constraint+0xf8/0xfc
__dev_pm_qos_update_request+0x138/0x164
dev_pm_qos_update_request+0x44/0x68
msm_devfreq_boost+0x40/0x70 [msm]
msm_devfreq_active+0xc0/0xf0 [msm]
msm_gpu_submit+0xc8/0x12c [msm]
msm_job_run+0x88/0x128 [msm]
drm_sched_main+0x240/0x324 [gpu_sched]
kthread+0xf0/0x100
ret_from_fork+0x10/0x20
other info that might help us debug this:
Chain exists of:
&devfreq->lock --> dev_pm_qos_mtx --> &(c->notifiers)->rwsem
Possible unsafe locking scenario:
CPU0 CPU1
---- ----
rlock(&(c->notifiers)->rwsem);
lock(dev_pm_qos_mtx);
lock(&(c->notifiers)->rwsem);
lock(&devfreq->lock);
*** DEADLOCK ***
4 locks held by ring0/391:
#0 : ffffff809c811170 (&gpu->lock){+.+.}-{3:3}, at: msm_job_run+0x7c/0x128 [msm]
#1 : ffffff809c811208 (&gpu->active_lock){+.+.}-{3:3}, at: msm_gpu_submit+0xa8/0x12c [msm]
#2 : ffffffecbbb46600 (dev_pm_qos_mtx){+.+.}-{3:3}, at: dev_pm_qos_update_request+0x38/0x68
#3 : ffffff809b8c1ce8 (&(c->notifiers)->rwsem){++++}-{3:3}, at: blocking_notifier_call_chain+0x34/0x78
stack backtrace:
CPU: 6 PID: 391 Comm: ring0 Not tainted 6.4.3debug+ #3
Hardware name: Google Villager (rev1+) with LTE (DT)
Call trace:
dump_backtrace+0xb4/0xf0
show_stack+0x20/0x30
dump_stack_lvl+0x60/0x84
dump_stack+0x18/0x24
print_circular_bug+0x1cc/0x234
check_noncircular+0x78/0xac
__lock_acquire+0xdf8/0x109c
lock_acquire+0x234/0x284
__mutex_lock+0xc8/0x388
mutex_lock_nested+0x2c/0x38
qos_notifier_call+0x30/0x74
qos_min_notifier_call+0x1c/0x28
notifier_call_chain+0xf4/0x114
blocking_notifier_call_chain+0x4c/0x78
pm_qos_update_target+0x184/0x190
freq_qos_apply+0x4c/0x64
apply_constraint+0xf8/0xfc
__dev_pm_qos_update_request+0x138/0x164
dev_pm_qos_update_request+0x44/0x68
msm_devfreq_boost+0x40/0x70 [msm]
msm_devfreq_active+0xc0/0xf0 [msm]
msm_gpu_submit+0xc8/0x12c [msm]
msm_job_run+0x88/0x128 [msm]
drm_sched_main+0x240/0x324 [gpu_sched]
kthread+0xf0/0x100
ret_from_fork+0x10/0x20
Fix this by only synchronizing access to gmu->initialized.
Fixes: 4cd15a3e8bdianders@chromium.org >
Signed-off-by: Rob Clark <robdclark@chromium.org >
Reviewed-by: Douglas Anderson <dianders@chromium.org >
Patchwork: https://patchwork.freedesktop.org/patch/551171/
2023-08-07 14:50:56 -07:00
Konrad Dybcio
29af760545
drm/msm/a6xx: Skip empty protection ranges entries
...
Some specific SKUs leave certain protection range registers empty.
Allow for that behavior.
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org >
Patchwork: https://patchwork.freedesktop.org/patch/543334/
Signed-off-by: Rob Clark <robdclark@chromium.org >
2023-08-07 14:30:49 -07:00
Konrad Dybcio
02a726fc6b
drm/msm/a6xx: Use descriptive bitfield names for CP_PROTECT_CNTL
...
We have the necessary information, so explain which bit does what.
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org >
Patchwork: https://patchwork.freedesktop.org/patch/543332/
Signed-off-by: Rob Clark <robdclark@chromium.org >
2023-08-07 14:30:49 -07:00
Rob Clark
47bd37f948
drm/msm/adreno: Move adreno info to config
...
Let's just stash it in adreno_platform_config rather than looking it up
in N different places.
Signed-off-by: Rob Clark <robdclark@chromium.org >
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org >
Patchwork: https://patchwork.freedesktop.org/patch/549777/
2023-08-07 14:21:19 -07:00
Rob Clark
c928a05e44
drm/msm/adreno: Move speedbin mapping to device table
...
This simplifies the code.
v2: Use a table of structs instead of flat uint32_t[]
Signed-off-by: Rob Clark <robdclark@chromium.org >
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org >
Patchwork: https://patchwork.freedesktop.org/patch/549769/
2023-08-07 14:19:16 -07:00
Rob Clark
459f9e26e7
drm/msm/adreno: Use quirk identify hw_apriv
...
Rather than just open coding a list of gpu-id matches.
Signed-off-by: Rob Clark <robdclark@chromium.org >
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org >
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org >
Patchwork: https://patchwork.freedesktop.org/patch/549764/
2023-08-07 14:19:16 -07:00
Rob Clark
f4f1c70781
drm/msm/adreno: Remove redundant revn param
...
This just duplicates what is in adreno_info, and can cause confusion if
used before it is set.
Signed-off-by: Rob Clark <robdclark@chromium.org >
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org >
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org >
Patchwork: https://patchwork.freedesktop.org/patch/549761/
2023-08-07 14:19:15 -07:00
Rob Clark
6391030df0
drm/msm/adreno: Remove redundant gmem size param
...
Even in the ocmem case, the allocated ocmem buffer size should match the
requested size.
v2: Move stray hunk to previous patch, make OCMEM size mismatch an error
condition.
Signed-off-by: Rob Clark <robdclark@chromium.org >
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org >
Patchwork: https://patchwork.freedesktop.org/patch/549759/
2023-08-07 14:19:15 -07:00
Konrad Dybcio
cd036d542a
drm/msm/a6xx: Add A610 speedbin support
...
A610 is implemented on at least three SoCs: SM6115 (bengal), SM6125
(trinket) and SM6225 (khaje). Trinket does not support speed binning
(only a single SKU exists) and we don't yet support khaje upstream.
Hence, add a fuse mapping table for bengal to allow for per-chip
frequency limiting.
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org >
Reviewed-by: Akhil P Oommen <quic_akhilpo@quicinc.com >
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org >
Patchwork: https://patchwork.freedesktop.org/patch/542780/
Signed-off-by: Rob Clark <robdclark@chromium.org >
2023-06-18 11:35:27 -07:00
Konrad Dybcio
20c8e39985
drm/msm/a6xx: Add A619_holi speedbin support
...
A619_holi is implemented on at least two SoCs: SM4350 (holi) and SM6375
(blair). This is what seems to be a first occurrence of this happening,
but it's easy to overcome by guarding the SoC-specific fuse values with
of_machine_is_compatible(). Do just that to enable frequency limiting
on these SoCs.
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org >
Reviewed-by: Akhil P Oommen <quic_akhilpo@quicinc.com >
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org >
Patchwork: https://patchwork.freedesktop.org/patch/542772/
Signed-off-by: Rob Clark <robdclark@chromium.org >
2023-06-18 11:35:27 -07:00
Konrad Dybcio
b3bcd583fa
drm/msm/a6xx: Use adreno_is_aXYZ macros in speedbin matching
...
Before transitioning to using per-SoC and not per-Adreno speedbin
fuse values (need another patchset to land elsewhere), a good
improvement/stopgap solution is to use adreno_is_aXYZ macros in
place of explicit revision matching. Do so to allow differentiating
between A619 and A619_holi.
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org >
Reviewed-by: Akhil P Oommen <quic_akhilpo@quicinc.com >
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org >
Patchwork: https://patchwork.freedesktop.org/patch/542777/
Signed-off-by: Rob Clark <robdclark@chromium.org >
2023-06-18 11:35:22 -07:00
Konrad Dybcio
ac92654965
drm/msm/a6xx: Use "else if" in GPU speedbin rev matching
...
The GPU can only be one at a time. Turn a series of ifs into if +
elseifs to save some CPU cycles.
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org >
Reviewed-by: Akhil P Oommen <quic_akhilpo@quicinc.com >
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org >
Patchwork: https://patchwork.freedesktop.org/patch/542770/
Signed-off-by: Rob Clark <robdclark@chromium.org >
2023-06-18 11:34:30 -07:00
Konrad Dybcio
3e90044d3e
drm/msm/a6xx: Fix some A619 tunables
...
Adreno 619 expects some tunables to be set differently. Make up for it.
Fixes: b7616b5c69dmitry.baryshkov@linaro.org >
Reviewed-by: Akhil P Oommen <quic_akhilpo@quicinc.com >
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org >
Patchwork: https://patchwork.freedesktop.org/patch/542782/
Signed-off-by: Rob Clark <robdclark@chromium.org >
2023-06-18 11:34:30 -07:00
Konrad Dybcio
e7fc9398e6
drm/msm/a6xx: Add A610 support
...
A610 is one of (if not the) lowest-tier SKUs in the A6XX family. It
features no GMU, as it's implemented solely on SoCs with SMD_RPM.
What's more interesting is that it does not feature a VDDGX line
either, being powered solely by VDDCX and has an unfortunate hardware
quirk that makes its reset line broken - after a couple of assert/
deassert cycles, it will hang for good and will not wake up again.
This GPU requires mesa changes for proper rendering, and lots of them
at that. The command streams are quite far away from any other A6XX
GPU and hence it needs special care. This patch was validated both
by running an (incomplete) downstream mesa with some hacks (frames
rendered correctly, though some instructions made the GPU hangcheck
which is expected - garbage in, garbage out) and by replaying RD
traces captured with the downstream KGSL driver - no crashes there,
ever.
Add support for this GPU on the kernel side, which comes down to
pretty simply adding A612 HWCG tables, altering a few values and
adding a special case for handling the reset line.
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org >
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org >
Patchwork: https://patchwork.freedesktop.org/patch/542779/
Signed-off-by: Rob Clark <robdclark@chromium.org >
2023-06-18 11:34:29 -07:00
Konrad Dybcio
8296ff0afd
drm/msm/a6xx: Add support for A619_holi
...
A619_holi is a GMU-less variant of the already-supported A619 GPU.
It's present on at least SM4350 (holi) and SM6375 (blair). No mesa
changes are required. Add the required kernel-side support for it.
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org >
Patchwork: https://patchwork.freedesktop.org/patch/542775/
Signed-off-by: Rob Clark <robdclark@chromium.org >
2023-06-18 11:34:29 -07:00
Konrad Dybcio
5a903a44a9
drm/msm/a6xx: Introduce GMU wrapper support
...
Some (particularly SMD_RPM, a.k.a non-RPMh) SoCs implement A6XX GPUs
but don't implement the associated GMUs. This is due to the fact that
the GMU directly pokes at RPMh. Sadly, this means we have to take care
of enabling & scaling power rails, clocks and bandwidth ourselves.
Reuse existing Adreno-common code and modify the deeply-GMU-infused
A6XX code to facilitate these GPUs. This involves if-ing out lots
of GMU callbacks and introducing a new type of GMU - GMU wrapper (it's
the actual name that Qualcomm uses in their downstream kernels).
This is essentially a register region which is convenient to model
as a device. We'll use it for managing the GDSCs. The register
layout matches the actual GMU_CX/GX regions on the "real GMU" devices
and lets us reuse quite a bit of gmu_read/write/rmw calls.
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org >
Patchwork: https://patchwork.freedesktop.org/patch/542766/
Signed-off-by: Rob Clark <robdclark@chromium.org >
2023-06-18 11:34:29 -07:00
Konrad Dybcio
30f55f3f23
drm/msm/a6xx: Move CX GMU power counter enablement to hw_init
...
Since the introduction of A6xx support, we've been enabling the CX GMU
power counter 0 in a bit of a weird spot. Move it to hw_init so that
GMU wrapper GPUs can reuse the same code paths. As a bonus, this order
makes it easier to compare mainline and downstream register access traces.
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org >
Patchwork: https://patchwork.freedesktop.org/patch/542765/
Signed-off-by: Rob Clark <robdclark@chromium.org >
2023-06-18 11:34:29 -07:00
Konrad Dybcio
df5bb404fa
drm/msm/a6xx: Extend and explain UBWC config
...
Rename lower_bit to hbb_lo and explain what it signifies.
Add explanations (wherever possible to other tunables).
Port setting min_access_length, ubwc_mode and hbb_hi from downstream.
Reviewed-by: Rob Clark <robdclark@gmail.com >
Reviewed-by: Akhil P Oommen <quic_akhilpo@quicinc.com >
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org >
Patchwork: https://patchwork.freedesktop.org/patch/542764/
Signed-off-by: Rob Clark <robdclark@chromium.org >
2023-06-18 11:34:29 -07:00
Konrad Dybcio
05a23a76d3
drm/msm/a6xx: Remove both GBIF and RBBM GBIF halt on hw init
...
Currently we're only deasserting REG_A6XX_RBBM_GBIF_HALT, but we also
need REG_A6XX_GBIF_HALT to be set to 0.
This is typically done automatically on successful GX collapse, but in
case that fails, we should take care of it.
Also, add a memory barrier to ensure it's gone through before jumping
to further initialization.
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org >
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org >
Patchwork: https://patchwork.freedesktop.org/patch/542760/
Signed-off-by: Rob Clark <robdclark@chromium.org >
2023-06-18 11:34:29 -07:00
Konrad Dybcio
277b967829
drm/msm/a6xx: Add a helper for software-resetting the GPU
...
Introduce a6xx_gpu_sw_reset() in preparation for adding GMU wrapper
GPUs and reuse it in a6xx_gmu_force_off().
This helper, contrary to the original usage in GMU code paths, adds
a readback+delay sequence to ensure that the reset is never deasserted
too quickly due to e.g. OoO execution going crazy.
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org >
Patchwork: https://patchwork.freedesktop.org/patch/542758/
Signed-off-by: Rob Clark <robdclark@chromium.org >
2023-06-18 11:34:29 -07:00
Konrad Dybcio
3773a57d9c
drm/msm/a6xx: Improve a6xx_bus_clear_pending_transactions()
...
Unify the indentation and explain the cryptic 0xF value.
Reviewed-by: Akhil P Oommen <quic_akhilpo@quicinc.com >
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org >
Patchwork: https://patchwork.freedesktop.org/patch/542756/
Signed-off-by: Rob Clark <robdclark@chromium.org >
2023-06-18 11:34:29 -07:00
Konrad Dybcio
6e332c99d1
drm/msm/a6xx: Move a6xx_bus_clear_pending_transactions to a6xx_gpu
...
This function is responsible for telling the GPU to halt transactions
on all of its relevant buses, drain them and leave them in a predictable
state, so that the GPU can be e.g. reset cleanly.
Move the function to a6xx_gpu.c, remove the static keyword and add a
prototype in a6xx_gpu.h to accomodate for the move.
Reviewed-by: Akhil P Oommen <quic_akhilpo@quicinc.com >
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org >
Patchwork: https://patchwork.freedesktop.org/patch/542762/
Signed-off-by: Rob Clark <robdclark@chromium.org >
2023-06-18 11:34:29 -07:00
Konrad Dybcio
ce8f1381fd
drm/msm/a6xx: Move force keepalive vote removal to a6xx_gmu_force_off()
...
As pointed out by Akhil during the review process of GMU wrapper
introduction [1], it makes sense to move this write into the function
that's responsible for forcibly shutting the GMU off.
It is also very convenient to move this to GMU-specific code, so that
it does not have to be guarded by an if-condition to avoid calling it
on GMU wrapper targets.
Move the write to the aforementioned a6xx_gmu_force_off() to achieve
that. No effective functional change.
[1] https://lore.kernel.org/linux-arm-msm/20230501194022.GA18382@akhilpo-linux.qualcomm.com/
Reviewed-by: Akhil P Oommen <quic_akhilpo@quicinc.com >
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org >
Patchwork: https://patchwork.freedesktop.org/patch/542752/
Signed-off-by: Rob Clark <robdclark@chromium.org >
2023-06-18 11:34:29 -07:00
Rob Clark
bf08e9791c
drm/msm/a6xx: Fix a690 CP_PROTECT settings
...
Allow access to CP_PERFCTR_CP_SEL[n] and RB_PERFCTR_RB_SEL which are
used by fdperf and pps-provider (perfetto).
Signed-off-by: Rob Clark <robdclark@chromium.org >
2023-06-10 06:46:12 -07:00
Bjorn Andersson
5e7665b5e4
drm/msm/adreno: Add Adreno A690 support
...
Introduce support for the Adreno A690, found in Qualcomm SC8280XP.
Tested-by: Steev Klimaszewski <steev@kali.org >
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org >
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org >
Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com >
Patchwork: https://patchwork.freedesktop.org/patch/540335/
Signed-off-by: Rob Clark <robdclark@chromium.org >
2023-06-10 06:46:12 -07:00
Dmitry Baryshkov
38e27a6fbf
drm/msm/a6xx: don't set IO_PGTABLE_QUIRK_ARM_OUTER_WBWA with coherent SMMU
...
If the Adreno SMMU is dma-coherent, allocation will fail unless we
disable IO_PGTABLE_QUIRK_ARM_OUTER_WBWA. Skip setting this quirk for the
coherent SMMUs (like we have on sm8350 platform).
Fixes: 54af0ceb75david@ixit.cz >
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org >
Tested-by: David Heidelberg <david@ixit.cz >
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org >
Tested-by: Konrad Dybcio <konrad.dybcio@linaro.org > # SM8450 HDK
Patchwork: https://patchwork.freedesktop.org/patch/531562/
Signed-off-by: Rob Clark <robdclark@chromium.org >
2023-06-10 06:46:12 -07:00
Dmitry Baryshkov
12abd735f0
drm/msm/a6xx: initialize GMU mutex earlier
...
Move GMU mutex initialization earlier to make sure that it is always
initialized. a6xx_destroy can be called from ther failure path before
GMU initialization.
This fixes the following backtrace:
------------[ cut here ]------------
DEBUG_LOCKS_WARN_ON(lock->magic != lock)
WARNING: CPU: 0 PID: 58 at kernel/locking/mutex.c:582 __mutex_lock+0x1ec/0x3d0
Modules linked in:
CPU: 0 PID: 58 Comm: kworker/u16:1 Not tainted 6.3.0-rc5-00155-g187c06436519 #565
Hardware name: Qualcomm Technologies, Inc. SM8350 HDK (DT)
Workqueue: events_unbound deferred_probe_work_func
pstate: 60400005 (nZCv daif +PAN -UAO -TCO -DIT -SSBS BTYPE=--)
pc : __mutex_lock+0x1ec/0x3d0
lr : __mutex_lock+0x1ec/0x3d0
sp : ffff800008993620
x29: ffff800008993620 x28: 0000000000000002 x27: ffff47b253c52800
x26: 0000000001000606 x25: ffff47b240bb2810 x24: fffffffffffffff4
x23: 0000000000000000 x22: ffffc38bba15ac14 x21: 0000000000000002
x20: ffff800008993690 x19: ffff47b2430cc668 x18: fffffffffffe98f0
x17: 6f74616c75676572 x16: 20796d6d75642067 x15: 0000000000000038
x14: 0000000000000000 x13: ffffc38bbba050b8 x12: 0000000000000666
x11: 0000000000000222 x10: ffffc38bbba603e8 x9 : ffffc38bbba050b8
x8 : 00000000ffffefff x7 : ffffc38bbba5d0b8 x6 : 0000000000000222
x5 : 000000000000bff4 x4 : 40000000fffff222 x3 : 0000000000000000
x2 : 0000000000000000 x1 : 0000000000000000 x0 : ffff47b240cb1880
Call trace:
__mutex_lock+0x1ec/0x3d0
mutex_lock_nested+0x2c/0x38
a6xx_destroy+0xa0/0x138
a6xx_gpu_init+0x41c/0x618
adreno_bind+0x188/0x290
component_bind_all+0x118/0x248
msm_drm_bind+0x1c0/0x670
try_to_bring_up_aggregate_device+0x164/0x1d0
__component_add+0xa8/0x16c
component_add+0x14/0x20
dsi_dev_attach+0x20/0x2c
dsi_host_attach+0x9c/0x144
devm_mipi_dsi_attach+0x34/0xac
lt9611uxc_attach_dsi.isra.0+0x84/0xfc
lt9611uxc_probe+0x5b8/0x67c
i2c_device_probe+0x1ac/0x358
really_probe+0x148/0x2ac
__driver_probe_device+0x78/0xe0
driver_probe_device+0x3c/0x160
__device_attach_driver+0xb8/0x138
bus_for_each_drv+0x84/0xe0
__device_attach+0x9c/0x188
device_initial_probe+0x14/0x20
bus_probe_device+0xac/0xb0
deferred_probe_work_func+0x8c/0xc8
process_one_work+0x2bc/0x594
worker_thread+0x228/0x438
kthread+0x108/0x10c
ret_from_fork+0x10/0x20
irq event stamp: 299345
hardirqs last enabled at (299345): [<ffffc38bb9ba61e4>] put_cpu_partial+0x1c8/0x22c
hardirqs last disabled at (299344): [<ffffc38bb9ba61dc>] put_cpu_partial+0x1c0/0x22c
softirqs last enabled at (296752): [<ffffc38bb9890434>] _stext+0x434/0x4e8
softirqs last disabled at (296741): [<ffffc38bb989669c>] ____do_softirq+0x10/0x1c
---[ end trace 0000000000000000 ]---
Fixes: 4cd15a3e8bdianders@chromium.org >
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org >
Reviewed-by: Douglas Anderson <dianders@chromium.org >
Patchwork: https://patchwork.freedesktop.org/patch/531540/
Signed-off-by: Rob Clark <robdclark@chromium.org >
2023-06-08 18:10:51 -07:00
Konrad Dybcio
63899a7319
drm/msm/a6xx: Add support for A650 speed binning
...
Add support for matching QFPROM fuse values to get the correct speed bin
on A650 (SM8250) GPUs.
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org >
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org >
Patchwork: https://patchwork.freedesktop.org/patch/530043/
Link: https://lore.kernel.org/r/20230331-topic-konahana_speedbin-v3-2-2dede22dd7f7@linaro.org
Signed-off-by: Rob Clark <robdclark@chromium.org >
2023-03-31 10:32:24 -07:00
Konrad Dybcio
9a06cd9a0f
drm/msm/a6xx: Add support for A640 speed binning
...
Add support for matching QFPROM fuse values to get the correct speed bin
on A640 (SM8150) GPUs.
Reviewed-by: Akhil P Oommen <quic_akhilpo@quicinc.com >
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org >
Patchwork: https://patchwork.freedesktop.org/patch/530042/
Link: https://lore.kernel.org/r/20230331-topic-konahana_speedbin-v3-1-2dede22dd7f7@linaro.org
Signed-off-by: Rob Clark <robdclark@chromium.org >
2023-03-31 10:32:13 -07:00
Dmitry Baryshkov
f62ad0f6f4
drm/msm/adreno: split a6xx fault handler into generic and a6xx parts
...
Split the a6xx_fault_handler() into the generic adreno_fault_handler()
and platform-specific parts. The adreno_fault_handler() can further be
used by a5xx and hopefully by a4xx (at some point).
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org >
Patchwork: https://patchwork.freedesktop.org/patch/522722/
Link: https://lore.kernel.org/r/20230214123504.3729522-3-dmitry.baryshkov@linaro.org
Signed-off-by: Rob Clark <robdclark@chromium.org >
2023-03-28 15:49:09 -07:00
Rob Clark
8ead967831
drm/msm/gpu: Move BO allocation out of hw_init
...
These allocations are only done the first (successful) time through
hw_init() so they won't actually happen in the job_run() path. But
lockdep doesn't know this. So dis-entangle them from the hw_init()
path.
Signed-off-by: Rob Clark <robdclark@chromium.org >
Patchwork: https://patchwork.freedesktop.org/patch/527852/
Link: https://lore.kernel.org/r/20230320144356.803762-14-robdclark@gmail.com
2023-03-25 16:31:45 -07:00
Rob Clark
f73343fae5
drm/msm: Update generated headers
...
It's been a bit overdue. Regen headers to pull in a2xx perfcntr
updates, etc.
Signed-off-by: Rob Clark <robdclark@chromium.org >
Patchwork: https://patchwork.freedesktop.org/patch/527926/
Link: https://lore.kernel.org/r/20230320185416.938842-2-robdclark@gmail.com
2023-03-21 09:10:47 -07:00
Rob Clark
f0c3a66f0e
drm/msm/a6xx: Some reg64 conversion
...
The next generated header update will drop the _LO/_HI suffix, now that
the userspace tooling properly understands 64b vs 32b regs (and the _LO/
_HI workarounds are getting cleaned up). So convert to using the 64b
reg helpers in prep.
Signed-off-by: Rob Clark <robdclark@chromium.org >
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org >
Patchwork: https://patchwork.freedesktop.org/patch/527923/
Link: https://lore.kernel.org/r/20230320185416.938842-1-robdclark@gmail.com
2023-03-20 14:13:51 -07:00
Akhil P Oommen
c11fa1204f
drm/msm/a6xx: Use genpd notifier to ensure cx-gdsc collapse
...
As per the recommended recovery sequence of adreno gpu, cx gdsc should
collapse at hardware before it is turned back ON. This helps to clear
out the stale states in hardware before it is reinitialized. Use the
genpd notifier along with the newly introduced
dev_pm_genpd_synced_poweroff() api to ensure that cx gdsc has collapsed
before we turn it back ON.
Signed-off-by: Akhil P Oommen <quic_akhilpo@quicinc.com >
Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org >
Patchwork: https://patchwork.freedesktop.org/patch/516472/
Link: https://lore.kernel.org/r/20230102161757.v5.5.I9e10545c6a448d5eb1b734839b871d1b3146dac3@changeid
Signed-off-by: Rob Clark <robdclark@chromium.org >
2023-03-20 10:54:22 -07:00
Akhil P Oommen
d484301225
drm/msm/a6xx: Remove cx gdsc polling using 'reset'
...
Remove the unused 'reset' interface which was supposed to help to ensure
that cx gdsc has collapsed during gpu recovery. This is was not enabled
so far due to missing gpucc driver support. Similar functionality using
genpd framework will be implemented in the upcoming patch.
This effectively reverts commit 1f6cca4049quic_akhilpo@quicinc.com >
Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org >
Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de >
Patchwork: https://patchwork.freedesktop.org/patch/516470/
Link: https://lore.kernel.org/r/20230102161757.v5.4.I96e0bf9eaf96dd866111c1eec8a4c9b70fd7cbcb@changeid
Signed-off-by: Rob Clark <robdclark@chromium.org >
2023-03-20 10:53:47 -07:00
Douglas Anderson
4cd15a3e8b
drm/msm/a6xx: Make GPU destroy a bit safer
...
If, for whatever reason, we're trying process adreno_runtime_resume()
at the same time that a6xx_destroy() is running then things can go
boom. Specifically adreno_runtime_resume() will eventually call
a6xx_pm_resume() and that may try to resume the gmu.
Let's grab the GMU lock as we're destroying the GMU. That will solve
the race because a6xx_pm_resume() grabs the same lock. That makes the
access of `gmu->initialized` in a6xx_gmu_resume() safe.
We'll also return an error code in a6xx_gmu_resume() if we see that
`gmu->initialized` was false. If this happens we'll bail out of the
rest of a6xx_pm_resume(), which is good because the rest of that
function is also not good to do if we're racing with a6xx_destroy().
Signed-off-by: Douglas Anderson <dianders@chromium.org >
Patchwork: https://patchwork.freedesktop.org/patch/521232/
Link: https://lore.kernel.org/r/20230202104822.1.I0e49003bf4dd1dead9be4a29dbee41f3b1236e48@changeid
Signed-off-by: Rob Clark <robdclark@chromium.org >
2023-02-22 11:22:03 -08:00
Dmitry Baryshkov
afd6dbfdfd
Merge branch 'msm-next-lumag' into HEAD
...
Merge display-related changes targeting Qualcomm DRM MSM driver.
Notable changes:
DPU, DSI, MDSS:
- Support for SM8350, SM8450 SM8550 and SC8280XP platform
Core:
- Added bindings for SM8150 (driver support already present)
DPU:
- Partial support for DSC on SM8150 and SM8250
- Fixed color transformation matrix being lost on suspend/resume
DP:
- Support for DP on SDM845 and SC8280XP platforms
- HPD fixes
- Support for limiting DP link rate via DT property, this enables
support for HBR3 rates.
DSI:
- Validate display modes according to the DSI OPP table
- DSI PHY support for the SM6375 platform
- Fixed byte intf clock selection for 14nm PHYs
MDP5:
- Schema conversion to YAML
Misc fixes as usual
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org >
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org >
2023-01-22 22:43:59 +02:00
Rob Clark
6563f60f14
drm/msm/gpu: Add devfreq tuning debugfs
...
Make the handful of tuning knobs available visible via debugfs.
v2: select DEVFREQ_GOV_SIMPLE_ONDEMAND because for some reason
struct devfreq_simple_ondemand_data depends on this
Signed-off-by: Rob Clark <robdclark@chromium.org >
Patchwork: https://patchwork.freedesktop.org/patch/517784/
Link: https://lore.kernel.org/r/20230110231447.1939101-2-robdclark@gmail.com
Reviewed-by: Chia-I Wu <olvaffe@gmail.com >
2023-01-16 10:40:18 -08:00
Akhil P Oommen
f4a75b5933
drm/msm/a6xx: Avoid gx gbit halt during rpm suspend
...
As per the downstream driver, gx gbif halt is required only during
recovery sequence. So lets avoid it during regular rpm suspend.
Signed-off-by: Akhil P Oommen <quic_akhilpo@quicinc.com >
Patchwork: https://patchwork.freedesktop.org/patch/515279/
Link: https://lore.kernel.org/r/20221216223253.1.Ice9c47bfeb1fddb8dc377a3491a043a3ee7fca7d@changeid
Signed-off-by: Rob Clark <robdclark@chromium.org >
2023-01-05 15:13:16 -08:00
Dave Airlie
077bd80083
Merge tag 'drm-msm-next-2022-11-28' of https://gitlab.freedesktop.org/drm/msm into drm-next
...
msm-next for v6.2 (the gpu/gem bits)
- Remove exclusive-fence hack that caused over-synchronization
- Fix speed-bin detection vs. probe-defer
- Enable clamp_to_idle on 7c3
- Improved hangcheck detection
Signed-off-by: Dave Airlie <airlied@redhat.com >
From: Rob Clark <robdclark@gmail.com >
Link: https://patchwork.freedesktop.org/patch/msgid/CAF6AEGvT1h_S4d=YRgphgR8i7aMaxQaNW8mru7QaoUo9uiUk2A@mail.gmail.com
2022-11-30 17:19:18 +10:00
Rob Clark
d73b1d02de
drm/msm: Hangcheck progress detection
...
If the hangcheck timer expires, check if the fw's position in the
cmdstream has advanced (changed) since last timer expiration, and
allow it up to three additional "extensions" to it's alotted time.
The intention is to continue to catch "shader stuck in a loop" type
hangs quickly, but allow more time for things that are actually
making forward progress.
Because we need to sample the CP state twice to detect if there has
not been progress, this also cuts the the timer's duration in half.
v2: Fix typo (REG_A6XX_CP_CSQ_IB2_STAT), add comment
v3: Only halve hangcheck timer duration for generations which
support progress detection (hdanton); removed unused a5xx
progress (without knowing how to adjust for data buffered
in ROQ it is too likely to report a false negative)
v4: Comment updates to better describe the total hangcheck
duration when progress detection is applied
Reviewed-by: Chia-I Wu <olvaffe@gmail.com >
Tested-by: Chia-I Wu <olvaffe@gmail.com > # dEQP-GLES2.functional.flush_finish.wait
Signed-off-by: Rob Clark <robdclark@chromium.org >
Reviewed-by: Akhil P Oommen <quic_akhilpo@quicinc.com >
Patchwork: https://patchwork.freedesktop.org/patch/511584/
Link: https://lore.kernel.org/r/20221114193049.1533391-3-robdclark@gmail.com
2022-11-17 10:39:12 -08:00
Rob Clark
cade05b2a8
drm/msm/adreno: Simplify read64/write64 helpers
...
The _HI reg is always following the _LO reg, so no need to pass these
offsets seprately.
Signed-off-by: Rob Clark <robdclark@chromium.org >
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org >
Reviewed-by: Akhil P Oommen <quic_akhilpo@quicinc.com >
Patchwork: https://patchwork.freedesktop.org/patch/511581/
Link: https://lore.kernel.org/r/20221114193049.1533391-2-robdclark@gmail.com
2022-11-17 10:39:12 -08:00
Rob Clark
2c1b774810
drm/msm: Enable clamp_to_idle for 7c3
...
This was overlooked.
Signed-off-by: Rob Clark <robdclark@chromium.org >
Reviewed-by: Douglas Anderson <dianders@chromium.org >
Reviewed-by: Chia-I Wu <olvaffe@gmail.com >
Patchwork: https://patchwork.freedesktop.org/patch/511693/
Link: https://lore.kernel.org/r/20221115155535.1615278-1-robdclark@gmail.com
2022-11-17 10:39:12 -08:00
Rob Clark
f6d1918794
drm/msm/a6xx: Fix speed-bin detection vs probe-defer
...
If we get an error (other than -ENOENT) we need to propagate that up the
stack. Otherwise if the nvmem driver hasn't probed yet, we'll end up
end up claiming that we support all the OPPs which is not likely to be
true (and on some generations impossible to be true, ie. if there are
conflicting OPPs).
v2: Update commit msg, gc unused label, etc
v3: Add previously missing \n's
Fixes: fe7952c629robdclark@chromium.org >
Reviewed-by: Douglas Anderson <dianders@chromium.org >
Reviewed-by: Akhil P Oommen <quic_akhilpo@quicinc.com >
Patchwork: https://patchwork.freedesktop.org/patch/511690/
Link: https://lore.kernel.org/r/20221115154637.1613968-1-robdclark@gmail.com
2022-11-17 10:39:06 -08:00
Dmitry Baryshkov
822ff993d3
drm/msm: remove duplicated code from a6xx_create_address_space
...
The function a6xx_create_address_space() is mostly a copy of
adreno_iommu_create_address_space() with added quirk setting. Rework
these two functions to be a thin wrappers around a common helper.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org >
Reviewed-by: Rob Clark <robdclark@gmail.com >
Patchwork: https://patchwork.freedesktop.org/patch/509614/
Link: https://lore.kernel.org/r/20221102175449.452283-3-dmitry.baryshkov@linaro.org
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org >
2022-11-03 02:23:46 +03:00
Dmitry Baryshkov
3236130b5d
drm/msm: move domain allocation into msm_iommu_new()
...
After the msm_iommu instance is created, the IOMMU domain is completely
handled inside the msm_iommu code. Move the iommu_domain_alloc() call
into the msm_iommu_new() to simplify callers code.
Reported-by: kernel test robot <lkp@intel.com >
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org >
Reviewed-by: Rob Clark <robdclark@gmail.com >
Patchwork: https://patchwork.freedesktop.org/patch/509615/
Link: https://lore.kernel.org/r/20221102175449.452283-2-dmitry.baryshkov@linaro.org
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org >
2022-11-03 02:23:45 +03:00
