The protocol converter configuration registers PCC8, PCCC, PCCD
(implemented by the driver), as well as others, control protocol
converters from multiple lanes (each represented as a different
struct phy). So, if there are simultaneous calls to phy_set_mode_ext()
to lanes sharing the same PCC register (either for the "old" or for the
"new" protocol), corruption of the values programmed to hardware is
possible, because lynx_28g_rmw() has no locking.
Add a spinlock in the struct lynx_28g_priv shared by all lanes, and take
the global spinlock from the phy_ops :: set_mode() implementation. There
are no other callers which modify PCC registers.
Fixes: 8f73b37cf3 ("phy: add support for the Layerscape SerDes 28G")
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
lynx_28g_cdr_lock_check() runs once per second in a workqueue to reset
the lane receiver if the CDR has not locked onto bit transitions in the
RX stream. But the PHY consumer may do stuff with the PHY simultaneously,
and that isn't okay. Block concurrent generic PHY calls by holding the
PHY mutex from this workqueue.
Fixes: 8f73b37cf3 ("phy: add support for the Layerscape SerDes 28G")
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
The blamed commit added the CDR check work item but didn't cancel it on
the remove path. Fix this by adding a remove function which takes care
of it.
Fixes: 8f73b37cf3 ("phy: add support for the Layerscape SerDes 28G")
Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Fix the following Smatch complaint:
drivers/phy/qualcomm/phy-qcom-m31.c:175 m31usb_phy_init()
warn: variable dereferenced before check 'qphy->vreg' (see line 167)
drivers/phy/qualcomm/phy-qcom-m31.c
166
167 ret = regulator_enable(qphy->vreg);
^^^^^^^^^^
Unchecked dereference
168 if (ret) {
169 dev_err(&phy->dev, "failed to enable regulator, %d\n", ret);
170 return ret;
171 }
172
173 ret = clk_prepare_enable(qphy->clk);
174 if (ret) {
175 if (qphy->vreg)
^^^^^^^^^^
Checked too late
176 regulator_disable(qphy->vreg);
177 dev_err(&phy->dev, "failed to enable cfg ahb clock, %d\n", ret);
Since the phy will not get registered if qphy->vreg is NULL,
this check is not needed.
Reported-by: Dan Carpenter <dan.carpenter@linaro.org>
Closes: https://lore.kernel.org/linux-phy/cbd26132-c624-44b7-a073-73222b287338@moroto.mountain/T/#u
Fixes: 08e49af507 ("phy: qcom: Introduce M31 USB PHY driver")
Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
Link: https://lore.kernel.org/r/1694069452-3794-1-git-send-email-quic_varada@quicinc.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Both debugfs_create_dir() and debugfs_create_file() return ERR_PTR
and never return NULL.
As Greg suggested, this patch removes the error checking for
debugfs_create_dir in phy-rtk-usb2.c and phy-rtk-usb3.c. This is because
the DebugFS kernel API is developed in a way that the caller can safely
ignore the errors that occur during the creation of DebugFS nodes. The
debugfs APIs have a IS_ERR() judge in start_creating() which can handle it
gracefully. So these checks are unnecessary.
Fixes: 134e6d25f6 ("phy: realtek: usb: Add driver for the Realtek SoC USB 2.0 PHY")
Fixes: adda6e82a7 ("phy: realtek: usb: Add driver for the Realtek SoC USB 3.0 PHY")
Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com>
Suggested-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Reviewed-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Link: https://lore.kernel.org/r/20230901075231.1368947-1-ruanjinjie@huawei.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Looks like the driver sleep pins configuration is unusable. Adding the
sleep pins causes the usb phy to not respond. We need to use the default
pins in probe, and only set sleep pins at phy_mdm6600_device_power_off().
As the modem can also be booted to a serial port mode for firmware
flashing, let's make the pin changes limited to probe and remove. For
probe, we get the default pins automatically. We only need to set the
sleep pins in phy_mdm6600_device_power_off() to prevent the modem from
waking up because the gpio line glitches.
If it turns out that we need a separate state for phy_mdm6600_power_on()
and phy_mdm6600_power_off(), we can use the pinctrl idle state.
Cc: Ivaylo Dimitrov <ivo.g.dimitrov.75@gmail.com>
Cc: Merlijn Wajer <merlijn@wizzup.org>
Cc: Pavel Machek <pavel@ucw.cz>
Cc: Sebastian Reichel <sre@kernel.org>
Fixes: 2ad2af0816 ("phy: mapphone-mdm6600: Improve phy related runtime PM calls")
Signed-off-by: Tony Lindgren <tony@atomide.com>
Reviewed-by: Sebastian Reichel <sebastian.reichel@collabora.com>
Link: https://lore.kernel.org/r/20230913060433.48373-3-tony@atomide.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Pull USB / Thunderbolt / PHY driver updates from Greg KH:
"Here is the big set of USB, Thunderbolt, and PHY driver updates for
6.6-rc1. Included in here are:
- PHY driver additions and cleanups
- Thunderbolt minor additions and fixes
- USB MIDI 2 gadget support added
- dwc3 driver updates and additions
- Removal of some old USB wireless code that was missed when that
codebase was originally removed a few years ago, cleaning up some
core USB code paths
- USB core potential use-after-free fixes that syzbot from different
people/groups keeps tripping over
- typec updates and additions
- gadget fixes and cleanups
- loads of smaller USB core and driver cleanups all over the place
Full details are in the shortlog. All of these have been in linux-next
for a while with no reported problems"
* tag 'usb-6.6-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb: (154 commits)
platform/chrome: cros_ec_typec: Configure Retimer cable type
tcpm: Avoid soft reset when partner does not support get_status
usb: typec: tcpm: reset counter when enter into unattached state after try role
usb: typec: tcpm: set initial svdm version based on pd revision
USB: serial: option: add FOXCONN T99W368/T99W373 product
USB: serial: option: add Quectel EM05G variant (0x030e)
usb: dwc2: add pci_device_id driver_data parse support
usb: gadget: remove max support speed info in bind operation
usb: gadget: composite: cleanup function config_ep_by_speed_and_alt()
usb: gadget: config: remove max speed check in usb_assign_descriptors()
usb: gadget: unconditionally allocate hs/ss descriptor in bind operation
usb: gadget: f_uvc: change endpoint allocation in uvc_function_bind()
usb: gadget: add a inline function gether_bitrate()
usb: gadget: use working speed to calcaulate network bitrate and qlen
dt-bindings: usb: samsung,exynos-dwc3: Add Exynos850 support
usb: dwc3: exynos: Add support for Exynos850 variant
usb: gadget: udc-xilinx: fix incorrect type in assignment warning
usb: gadget: udc-xilinx: fix cast from restricted __le16 warning
usb: gadget: udc-xilinx: fix restricted __le16 degrades to integer warning
USB: dwc2: hande irq on dead controller correctly
...
Pull clk subsystem updates from Stephen Boyd:
"This pull request is full of clk driver changes. In fact, there aren't
any changes to the clk framework this time around. That's probably
because everyone was on vacation (yours truly included). We did lose a
couple clk drivers this time around because nobody was using those
devices. That skews the diffstat a bit, but either way, nothing looks
out of the ordinary here. The usual suspects are chugging along adding
support for more SoCs and fixing bugs.
If I had to choose, I'd say the theme for the past few months has been
"polish". There's quite a few patches that migrate to
devm_platform_ioremap_resource() in here. And there's more than a
handful of patches that move the NR_CLKS define from the DT binding
header to the driver. There's even patches that migrate drivers to use
clk_parent_data and clk_hw to describe clk tree topology. It seems
that the spring (summer?) cleaning bug got some folks, or the
semiconductor shortage finally hit the software side.
New Drivers:
- StarFive JH7110 SoC clock drivers
- Qualcomm IPQ5018 Global Clock Controller driver
- Versa3 clk generator to support 48KHz playback/record with audio
codec on RZ/G2L SMARC EVK
Removed Drivers:
- Remove non-OF mmp clk drivers
- Remove OXNAS clk driver
Updates:
- Add __counted_by to struct clk_hw_onecell_data and struct
spmi_pmic_div_clk_cc
- Move defines for numbers of clks (NR_CLKS) from DT headers to
drivers
- Introduce kstrdup_and_replace() and use it
- Add PLL rates for Rockchip rk3568
- Add the display clock tree for Rockchip rv1126
- Add Audio Clock Generator (ADG) clocks on Renesas R-Car Gen3 and
RZ/G2 SoCs
- Convert sun9i-mmc clock to use
devm_platform_get_and_ioremap_resource()
- Fix function name in a comment in ccu_mmc_timing.c
- Parameter name correction for ccu_nkm_round_rate()
- Implement CLK_SET_RATE_PARENT for Allwinner NKM clocks, i.e.
consider alternative parent rates when determining clock rates
- Set CLK_SET_RATE_PARENT for Allwinner A64 pll-mipi
- Support finding closest (as opposed to closest but not higher)
clock rate for NM, NKM, mux and div type clocks, as use it for
Allwinner A64 pll-video0
- Prefer current parent rate if able to generate ideal clock rate for
Allwinner NKM clocks
- Clean up Qualcomm SMD RPM driver, with interconnect bus clocks
moved out to the interconnect drivers
- Fix various PM runtime bugs across many Qualcomm clk drivers
- Migrate Qualcomm MDM9615 is to parent_hw and parent_data
- Add network related resets on Qualcomm IPQ4019
- Add a couple missing USB related clocks to Qualcomm IPQ9574
- Add missing gpll0_sleep_clk_src to Qualcomm MSM8917 global clock
controller
- In the Qualcomm QDU1000 global clock controller, GDSCs, clkrefs,
and GPLL1 are added, while PCIe pipe clock, SDCC rcg ops are
corrected
- Add missing GDSCs to and correct GDSCs for the SC8280XP global
clock controller driver
- Support retention for the Qualcomm SC8280XP display clock
controller GDSCs.
- Qualcommm's SDCC apps_clk_src is marked with CLK_OPS_PARENT_ENABLE
to fix issues with missing parent clocks across sc7180, sm7150,
sm6350 and sm8250, while sm8450 is corrected to use floor ops
- Correct Qualcomm SM6350 GPU clock controller's clock supplies
- Drop unwanted clocks from the Qualcomm IPQ5332 GCC driver
- Add missing OXILICX GDSC to Qualcomm MSM8226 GCC
- Change the delay in the Qualcomm reset controller to fsleep() for
correctness
- Extend the Qualcomm SM83550 Video clock controller to support
SC8280XP
- Add graphics clock support on Renesas RZ/G2M, RZ/G2N, RZ/G2E, and
R-Car H3, M3-W, and M3-N SoCs
- Add Clocked Serial Interface (CSI) clocks on Renesas RZ/V2M
- Add PWM (MTU3) clock and reset on Renesas RZ/G2UL and RZ/Five
- Add the PDM IPC clock for i.MX93
- Add 519.75MHz frequency support for i.MX9 PLL
- Simplify the .determine_rate() implementation for i.MX GPR mux
- Make the i.MX8QXP LPCG clock use devm_platform_ioremap_resource()
- Add the audio mux clock to i.MX8
- Fix the SPLL2 MULT range for PLLv4
- Update the SPLL2 type in i.MX8ULP
- Fix the SAI4 clock on i.MX8MP
- Add silicon revision print for i.MX25 on clocks init
- Drop the return value from __mx25_clocks_init()
- Fix the clock pauses on no-op set_rate for i.MX8M composite clock
- Drop restrictions for i.MX PLL14xx and fix its max prediv value
- Drop the 393216000 and 361267200 from i.MX PLL14xx rate table to
allow glitch free switching"
* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (207 commits)
clk: qcom: Fix SM_GPUCC_8450 dependencies
clk: lmk04832: Support using PLL1_LD as SPI readback pin
clk: lmk04832: Don't disable vco clock on probe fail
clk: lmk04832: Set missing parent_names for output clocks
clk: mvebu: Convert to devm_platform_ioremap_resource()
clk: nuvoton: Convert to devm_platform_ioremap_resource()
clk: socfpga: agilex: Convert to devm_platform_ioremap_resource()
clk: ti: Use devm_platform_get_and_ioremap_resource()
clk: mediatek: Convert to devm_platform_ioremap_resource()
clk: hsdk-pll: Convert to devm_platform_ioremap_resource()
clk: gemini: Convert to devm_platform_ioremap_resource()
clk: fsl-sai: Convert to devm_platform_ioremap_resource()
clk: bm1880: Convert to devm_platform_ioremap_resource()
clk: axm5516: Convert to devm_platform_ioremap_resource()
clk: actions: Convert to devm_platform_ioremap_resource()
clk: cdce925: Remove redundant of_match_ptr()
clk: pxa910: Move number of clocks to driver source
clk: pxa1928: Move number of clocks to driver source
clk: pxa168: Move number of clocks to driver source
clk: mmp2: Move number of clocks to driver source
...
Implement Exynos850 USB 2.0 DRD PHY controller support. Exynos850 has
quite a different PHY controller than Exynos5 compatible controllers,
but it's still possible to implement it on top of existing
exynos5-usbdrd driver infrastructure.
Only UTMI+ (USB 2.0) PHY interface is implemented, as Exynos850 doesn't
support USB 3.0.
Only two clocks are used for this controller:
- phy: bus clock, used for PHY registers access
- ref: PHY reference clock (OSCCLK)
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20230819031731.22618-7-semen.protsenko@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Modern Exynos chips (like Exynos850) might have 26 MHz OSCCLK external
clock, which is also used as a PHY reference clock. For some USB PHY
controllers (e.g USB DRD PHY block on Exynos850) there is no need to set
the refclk frequency at all (and corresponding bits in CLKRSTCTRL[7:5]
are marked RESERVED), so that value won't be set in the driver. But
even in that case, 26 MHz support still has to be added, otherwise
exynos5_rate_to_clk() fails, which leads in turn to probe error.
Add the correct value for 26MHz refclk to make it possible to add
support for new Exynos USB DRD PHY controllers.
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20230819031731.22618-6-semen.protsenko@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
During rebase of qcom-qmp-combo series a call to devm_clk_bulk_get_all()
got moved by git from qmp_combo_parse_dt_legacy() to
phy_dp_clks_register(). This doesn't have any serious effect, since the
clocks will be set in both legacy and non-legacy paths. However let's
move it back to place anyway, to prevent the driver from fetching clocks
twice.
Fixes: 28e265bf84 ("phy: qcom-qmp-combo: simplify clock handling")
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20230820235813.562284-1-dmitry.baryshkov@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
We need the USB fixes in here for testing and for other patches to be
applied on top of.
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
When USB_COMMON are not enabled, phy-rtk-usb2 and phy-rtk-usb3 suffers
a build error due to a missing usb_debug_root that is provided
by CONFIG_USB_COMMON, so make the driver select USB_COMMON.
or1k-linux-ld: drivers/phy/realtek/phy-rtk-usb2.o: in function `create_phy_debug_root':
>> drivers/phy/realtek/phy-rtk-usb2.c:715: undefined reference to `usb_debug_root'
>> or1k-linux-ld: drivers/phy/realtek/phy-rtk-usb2.c:715: undefined reference to `usb_debug_root'
or1k-linux-ld: drivers/phy/realtek/phy-rtk-usb3.o: in function `create_phy_debug_root':
>> drivers/phy/realtek/phy-rtk-usb3.c:349: undefined reference to `usb_debug_root'
>> or1k-linux-ld: drivers/phy/realtek/phy-rtk-usb3.c:349: undefined reference to `usb_debug_root'
Fixes: 134e6d25f6 ("phy: realtek: usb: Add driver for the Realtek SoC USB 2.0 PHY")
Fixed: adda6e82a7 ("phy: realtek: usb: Add driver for the Realtek SoC USB 3.0 PHY")
Reported-by: kernel test robot <lkp@intel.com>
Closes: https://lore.kernel.org/oe-kbuild-all/202307290733.weSlHrGp-lkp@intel.com/
Closes: https://lore.kernel.org/oe-kbuild-all/202307291022.3pVeTR9z-lkp@intel.com/
Signed-off-by: Stanley Chang <stanley_chang@realtek.com>
Link: https://lore.kernel.org/r/20230729053029.6226-1-stanley_chang@realtek.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
