3 Commits

Author	SHA1	Message	Date
Thierry Reding	67a82dbc0a	gpu: host1x: Support 40-bit addressing ... Tegra186 and later support 40 bits of address space. Additional registers need to be programmed to store the full 40 bits of push buffer addresses. Since command stream gathers can also reside in buffers in a 40-bit address space, a new variant of the GATHER opcode is also introduced. It takes two parameters: the first parameter contains the lower 32 bits of the address and the second parameter contains bits 32 to 39. Signed-off-by: Thierry Reding <treding@nvidia.com>	2019-02-07 18:28:35 +01:00
Thierry Reding	de5469c21f	gpu: host1x: Program the channel stream ID ... When processing command streams, make sure the host1x's stream ID is programmed for the channel so that addresses are properly translated through the SMMU. Signed-off-by: Thierry Reding <treding@nvidia.com>	2019-02-07 18:28:33 +01:00
Thierry Reding	ac1bdbf22b	gpu: host1x: Add Tegra194 support ... The host1x hardware found on Tegra194 is mostly backwards compatible with the version found on Tegra186, with the notable exceptions of the increased number of syncpoints and mlocks. In addition, some rarely used features such as syncpoint wait bases were dropped and some registers had to move around to accomodate the increased number of syncpoints. Signed-off-by: Thierry Reding <treding@nvidia.com>	2018-11-29 17:11:49 +01:00