Let's use the pci/platform-specialized functions for mapping a resource,
and pass the mapped address to intel_spi_probe. Benefits are:
- No separate call needed for getting the resource, and no access to
struct pci_dev internals (pdev->resource[]).
- More user-friendly output in /proc/iomem. In my case:
before
80704000-80704fff : 0000:00:1f.5
80704000-80704fff : 0000:00:1f.5 0000:00:1f.5
after
80704000-80704fff : 0000:00:1f.5
80704000-80704fff : spi_intel_pci
Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com>
Link: https://patch.msgid.link/2585fa05-60c4-48c4-a838-e87014665ae2@gmail.com
Signed-off-by: Mark Brown <broonie@kernel.org>
The manufacturing access to the PCH/SoC SPI device is traditionally
performed via userspace driver accessing registers via /dev/mem but due
to security concerns /dev/mem access is being much restricted, hence the
reason for utilizing dedicated Intel PCH/SoC SPI controller driver,
which is already implemented in the Linux kernel.
Intel PCH/SoC SPI controller protects the flash storage via two
mechanisms one is the via region protection registers and second via
BIOS lock. The BIOS locks only the BIOS regions usually 0 and/or 6.
The device always boots with BIOS lock set, but during manufacturing the
BIOS lock has to be lifted in order to enable the write access. This can
be done by passing "writeable=1" in the command line when the driver is
loaded. This "locked" state is exposed through new sysfs attributes
(intel_spi_locked, intel_spi_bios_locked).
Second, also the region protection status is exposed via sysfs attribute
(intel_spi_protected) as the manufacturing will need the both files in
order to validate that the device is properly sealed.
Includes code written by Tamar Mashiah.
Signed-off-by: Alexander Usyskin <alexander.usyskin@intel.com>
Co-developed-by: Tomas Winkler <tomasw@gmail.com>
Signed-off-by: Tomas Winkler <tomasw@gmail.com>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Link: https://patch.msgid.link/20241009062244.2436793-1-mika.westerberg@linux.intel.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Some private data fields have to change from bxt_info to cnl_info.
Here is the list of Device IDs with the respective documentation taken for
validation:
0xa0a4 - Intel® 500 Series Chipset Family On-Package PCH
0x02a4 - Intel® 400 Series Chipset Family On-Package PCH
0x06a4 - Intel® 400 Series Chipset Family Platform Controller Hub
0x34a4 - Intel® 495 Chipset Family On-Package
0xa3a4 - Intel® B460 and H410 Chipset
According to documentation Broxton controller type has five PR registers.
Signed-off-by: Mauro Lima <mauro.lima@eclypsium.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Link: https://lore.kernel.org/r/20230201205455.550308-2-mauro.lima@eclypsium.com
Signed-off-by: Mark Brown <broonie@kernel.org>
