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307 Commits

Author SHA1 Message Date
James Zhu
467db422cb drm/amdgpu/vcn: enable VCN DPG mode for dimgrey_cavefish 
Enable VCN DPG mode for dimgrey_cavefish.

Signed-off-by: James Zhu <James.Zhu@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-10-12 14:00:54 -04:00
Tao Zhou
76a2d9ea69 drm/amdgpu: add virtual display support for dimgrey_cavefish 
Add virtual ip block for dimgrey_cavefish.

Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Jiansong Chen <Jiansong.Chen@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-10-12 14:00:45 -04:00
Tao Zhou
0106922600 drm/amdgpu: add sdma ip block for dimgrey_cavefish 
Enable sdma block for dimgrey_cavefish, same as sienna_cichlid.

Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Jiansong Chen <Jiansong.Chen@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-10-12 14:00:37 -04:00
Tao Zhou
feb6329c58 drm/amdgpu: add gfx ip block for dimgrey_cavefish 
Enable gfx block for dimgrey_cavefish, same as navy_flounder.

Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Jiansong Chen <Jiansong.Chen@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-10-12 14:00:35 -04:00
Tao Zhou
771cc67ed0 drm/amdgpu: add ih ip block for dimgrey_cavefish 
Enable ih block for dimgrey_cavefish, same as navy_flounder.

Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Jiansong Chen <Jiansong.Chen@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-10-12 14:00:31 -04:00
Tao Zhou
3e02ad4476 drm/amdgpu: add gmc ip block for dimgrey_cavefish 
Enable gmc block for dimgrey_cavefish, same as sienna_cichlid.

Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Jiansong Chen <Jiansong.Chen@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-10-12 14:00:29 -04:00
Tao Zhou
2aa92b12df drm/amdgpu: add common ip block for dimgrey_cavefish 
Same as navy_flounder.

Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Jiansong Chen <Jiansong.Chen@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-10-12 14:00:25 -04:00
Tao Zhou
038d757b95 drm/amdgpu: initialize IP offset for dimgrey_cavefish 
Add ip offset definition for dimgrey_cavefish and initialize it.

Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Jiansong Chen <Jiansong.Chen@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-10-12 14:00:20 -04:00
Tao Zhou
550c58e0fa drm/amdgpu: add common support for dimgrey_cavefish 
Add external id and set clock gating for dimgrey_cavefish.

Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Jiansong Chen <Jiansong.Chen@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-10-12 14:00:18 -04:00
Huang Rui
ac0dc4c5a0 drm/amdgpu: enable gfx clock gating and power gating for vangogh 
This patch is to enable the gfx cg and pg for vangogh.

Signed-off-by: Huang Rui <ray.huang@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-10-05 15:15:28 -04:00
Alex Deucher
8bb3aa1a83 drm/amdgpu: IP discovery table is not ready yet for VG 
Fallback to legacy path for now.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-10-05 15:15:28 -04:00
Huang Rui
ed3b735332 drm/amdgpu: enable psp support for vangogh 
This patch is to enable psp support for vangogh

Signed-off-by: Huang Rui <ray.huang@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-10-05 15:15:28 -04:00
Huang Rui
c821e0fbb2 drm/amdgpu: add smu ip block for vangogh 
This patch is to add ip block for vangogh.

Signed-off-by: Huang Rui <ray.huang@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Aaron Liu <aaron.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-10-05 15:15:27 -04:00
Huang Rui
a7e91bd718 drm/amdgpu: add nbio v7.2 for vangogh (v2) 
VanGogh uses nbio v7.2, and a couple of offsets are changed since nbio
v2.3 for navi series, so add new nbio v7.2 block.

v2: squash in fix for sdma and vcn instances

Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-10-05 15:15:27 -04:00
Huang Rui
5de54343d5 drm/amdgpu: add pcie port indirect read and write on nv 
This patch is to add pcie port indirect read/write callback for nv
series. They will be used for new asic.

Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-10-05 15:15:27 -04:00
Thong Thai
b4e532d678 drm/amdgpu: enable vcn3.0 for van gogh 
Same as other VCN 3.0 asics.

Signed-off-by: Thong Thai <thong.thai@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-10-05 15:15:27 -04:00
Huang Rui
88edbad6ed drm/amdgpu: set ip blocks for van gogh 
Enable ip blocks for van gogh.

Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-10-05 15:15:27 -04:00
Huang Rui
fced3c3a46 drm/amdgpu: skip sdma1 in nv_allowed_read_registers list for van gogh (v2) 
Van gogh only has one sdma.

v2: use num_instances rather than APU flag

Signed-off-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-10-05 15:14:03 -04:00
Huang Rui
026570e633 drm/amdgpu: add nv common ip block support for van gogh 
This patch adds common ip support for van gogh.

Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-10-05 15:14:02 -04:00
Hawking Zhang
705a2b5ba0 drm/amdgpu: switch to indirect reg access helper 
Switch WREG32/RREG32_PCIE to use indirect reg access
helper for soc15 and onwards

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Guchun Chen <guchun.chen@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-10-01 10:42:48 -04:00
Stanley.Yang
78f0aef11f drm/amdgpu: fix hdp register access error 
mmHDP_READ_CACHE_INVALIDATE register is in HDP not in NBIO

Signed-off-by: Stanley.Yang <Stanley.Yang@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-09-22 17:37:38 -04:00
Andrey Grodzovsky
c1dd4aa624 drm/amdgpu: Fix consecutive DPC recovery failures. 
Cache the PCI state on boot and before each case where we might
loose it.

v2: Add pci_restore_state while caching the PCI state to avoid
breaking PCI core logic for stuff like suspend/resume.

v3: Extract pci_restore_state from amdgpu_device_cache_pci_state
to avoid superflous restores during GPU resets and suspend/resumes.

v4: Style fixes.

Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-09-15 17:25:04 -04:00
Jiansong Chen
22dd44f47c drm/amdgpu: use MODE1 reset for navy_flounder by default 
Switch default gpu reset method to MODE1 for navy_flounder.

Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-08-26 16:40:19 -04:00
Alex Deucher
a71737313e drm/amdgpu: add pre_asic_init callback for navi 
Nothing to do for this family.

Acked-by: Nirmoy Das <nirmoy.das@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-08-26 16:40:19 -04:00
Alex Deucher
11043b7a99 drm/amdgpu: note what type of reset we are using 
When we reset the GPU, note what type of reset will be
used.  This makes debugging different reset scenarios
more clear as the driver may use different reset
methods depending on conditions on the system.

Acked-by: Nirmoy Das <nirmoy.das@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-08-14 17:03:20 -04:00
Likun Gao
ca6fd7a668 drm/amdgpu: use mode1 reset by default for sienna_cichlid 
Swith default gpu reset method for sienna_cichlid to MODE1 reset.

Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-08-07 17:29:29 -04:00
John Clements
4922f1bcad drm/amdgpu: expand sienna chichlid reg access support 
Added dedicated 64bit reg read/write support

Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: John Clements <john.clements@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-22 18:42:09 -04:00
John Clements
c652923afa drm/amdgpu: enable xgmi support for sienna cichlid 
set xgmi support flag suring nv ip init sequence

Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: John Clements <john.clements@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-21 15:37:39 -04:00
Jiansong Chen
85e7151baa drm/amdgpu: enable ih CG for navy_flounder 
Enable ih CG by setting the corresponding flag.

Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-15 13:27:34 -04:00
Jiansong Chen
4759f8871f drm/amdgpu: enable hdp CG and LS for navy_flounder 
Enable hdp CG and LS by setting the corresponding flags.

Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-15 13:27:34 -04:00
Jiansong Chen
92c737561c drm/amdgpu: enable mc CG and LS for navy_flounder 
Enable mc CG and LS by setting the corresponding flags.

Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-15 13:27:34 -04:00
Jiansong Chen
47fc894a87 drm/amdgpu: enable athub/mmhub PG for navy_flounder 
Enable athub/mmhub PG by setting the corresponding flags.
Actually the enablement is exercised by PMFW.

Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-15 13:27:34 -04:00
Bhawanpreet Lakha
a6c5308f2a drm/amd/display: add DC support for navy flounder 
Plumb DC support for navy flounder through.

Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-15 13:27:26 -04:00
Jiansong Chen
40582e670f drm/amdgpu: enable GFX clock gating for navy_flounder 
Enable GFX MGCG, CGCG and 3DCG for navy_flounder.

Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-15 12:47:21 -04:00
Boyuan Zhang
00740df995 drm/amdgpu: enable JPEG3.0 PG and CG for navy_flounder 
Enable JPEG3.0 PG and CG for navy_flounder by setting up the flags to the ASIC

Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-15 12:47:17 -04:00
Boyuan Zhang
c6e9dd0ea8 drm/amdgpu: enable VCN3.0 DPG for navy_flounder 
Enable VCN3.0 DPG for navy_flounder by setting up the flag to the ASIC

Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-15 12:47:14 -04:00
Boyuan Zhang
ebb06097ee drm/amdgpu: enable VCN3.0 PG and CG for navy_flounder 
Enable VCN3.0 PG and CG for navy_flounder by setting up the flags to the ASIC

Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-15 12:47:12 -04:00
Boyuan Zhang
290b4ad592 drm/amdgpu: add vcn ip block for navy_flounder 
Add vcn3.0 and jpeg3.0 ip blocks for navy_flounder

Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-15 12:47:06 -04:00
Jiansong Chen
7420eab23b drm/amdgpu: add psp block for navy_flounder 
Add psp and smu block for navy_flounder with
psp firmware load type.

Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-15 12:46:50 -04:00
Jiansong Chen
f4497d1029 drm/amdgpu: add smu block for navy_flounder 
Add SMU block for navy_flounder with direct
firmware load type.

Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-15 12:46:44 -04:00
Jiansong Chen
5404f07359 drm/amdgpu: add virtual display support for navy_flounder. 
Virtual display support for bring up and virtualization.

Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-15 12:46:29 -04:00
Jiansong Chen
df2d15df04 drm/amdgpu: add sdma ip block for navy_flounder 
Navy_Flounder has the same sdma IP version with
sienna_cichlid, and it has 2 sdma controllers.

Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-15 12:46:26 -04:00
Jiansong Chen
885eb3fad6 drm/amdgpu: add gfx ip block for navy_flounder 
since navy_flounder has similar gc IP version with
sienna_cichlid, follow its setting for the moment.

Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com>
Reviewed-by: Tao Zhou <Tao.Zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-15 12:46:23 -04:00
Jiansong Chen
026c396b41 drm/amdgpu: add ih ip block for navy_flounder 
navy_flounder has the same osssys IP verison with
sienna_cichlid, follow its setting.

Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com>
Reviewed-by: Tao Zhou <Tao.Zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-15 12:46:19 -04:00
Jiansong Chen
fc8f07da1f drm/amdgpu: add gmc ip block for navy_flounder 
navy_flounder has similar gc IP version with sienna_cichlid,
follow its setting for the moment.

Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com>
Reviewed-by: Tao Zhou <Tao.Zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-15 12:46:14 -04:00
Jiansong Chen
8515e0a489 drm/amdgpu: add common ip block for navy_flounder 
Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com>
Reviewed-by: Tao Zhou <Tao.Zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-15 12:46:11 -04:00
Jiansong Chen
c8c959f601 drm/amdgpu: initialize IP offset for navy_flounder 
since navy_flounder has the same ip offset with sienna_cichlid,
follow sienna_cichlid setting for the moment.

Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com>
Reviewed-by: Tao Zhou <Tao.Zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-15 12:46:07 -04:00
Jiansong Chen
543aa2595c drm/amdgpu/soc15: add support for navy_flounder 
Add soc support.

Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com>
Reviewed-by: Tao Zhou <Tao.Zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-15 12:46:00 -04:00
Jack Zhang
c45fbe1bd5 drm/amd/sriov skip jped ip block and close pgcg flags 
For SIENNA_CICHLID SRIOV, jpeg and pgcp is not supported.

Signed-off-by: Jack Zhang <Jack.Zhang1@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-15 12:44:53 -04:00
Wenhui Sheng
273da6ff7c drm/amdgpu: add module parameter choose reset mode 
Default value is auto, doesn't change
original reset method logic.

v2: change to use parameter reset_method
v3: add warn msg if specified mode isn't supported

Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Wenhui Sheng <Wenhui.Sheng@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-15 12:42:01 -04:00