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1132 Commits

Author SHA1 Message Date
Pratap Nirujogi
0253d718a0 drm/amd/amdgpu: Map ISP interrupts as generic IRQs 
Map ISP IH interrupts to Linux generic IRQ for ISP driver to
handle the interrupts using MFD IORESOURCE_IRQ resource.

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Mario Limonciello <mario.limonciello@amd.com>
Signed-off-by: Pratap Nirujogi <pratap.nirujogi@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2024-06-27 17:34:40 -04:00
Pratap Nirujogi
772e4d56da drm/amd/amdgpu: Add ISP support to amdgpu_discovery 
ISP hw block is supported in some of the AMD GPU versions, add support
to discover ISP IP in amdgpu_discovery.

v2: squash in documentation update (Alex)

Reviewed-by: Mario Limonciello <mario.limonciello@amd.com>
Signed-off-by: Pratap Nirujogi <pratap.nirujogi@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2024-06-27 17:34:39 -04:00
Aurabindo Pillai
ad89e904e3 drm/amd: Add some missing register definitions 
Add some register offsets that are required for Display DCC on DCN401

Fixes: 2d072b4456 ("drm/amd: Add reg definitions for DCN401 DCC")
Reported-by: Tom St Denis <tom.stdenis@amd.com>
Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2024-06-27 17:32:17 -04:00
Aurabindo Pillai
2d072b4456 drm/amd: Add reg definitions for DCN401 DCC 
[WHAT]
Add the necessary register definitions to enable DCC on DCN4x

Reviewed-by: Rodrigo Siqueira <rodrigo.siqueira@amd.com>
Signed-off-by: Alex Hung <alex.hung@amd.com>
Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2024-06-27 17:10:38 -04:00
Frank Min
3c7758beb2 drm/amdgpu: Update soc24_enum.h and soc21_enum.h 
Update to latest changes.

Signed-off-by: Frank Min <Frank.Min@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2024-06-05 11:25:14 -04:00
Alex Deucher
b592d01df6 drm/amdgpu: update gc_12_0_0 headers 
Add some additional registers.

Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2024-06-05 11:03:10 -04:00
Tasos Sahanidis
98f9e5ea47 drm/amdgpu/pptable: Fix UBSAN array-index-out-of-bounds 
Flexible arrays used [1] instead of []. Replace the former with the latter
to resolve multiple UBSAN warnings observed on boot with a BONAIRE card.

In addition, use the __counted_by attribute where possible to hint the
length of the arrays to the compiler and any sanitizers.

Signed-off-by: Tasos Sahanidis <tasos@tasossah.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2024-06-05 11:02:24 -04:00
Rodrigo Siqueira
d0a6d85072 drm/amd/display: Add missing registers for DCN401 
Add some additional registers.

Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2024-05-29 14:40:39 -04:00
Alex Deucher
f2a1fbdd1f drm/amdgpu: drop MES 10.1 support v3 
It was an enablement vehicle for MES 11 and was never
productized.  Remove it.

v2: drop additional checks in the GFX10 code.
v3: drop mes_api_def.h

Acked-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Harish Kasiviswanathan <Harish.Kasiviswanathan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2024-05-29 14:09:01 -04:00
Alex Deucher
ca0bfaad4f drm/amdgpu: silence UBSAN warning 
Convert a variable sized array from [1] to [].

Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2024-05-29 14:08:53 -04:00
Sunil Khatri
eb14b8f505 drm/amdgpu: Add missing offsets in gc_11_0_0_offset.h 
IB1 registers:
regCP_IB1_CMD_BUFSZ
regCP_IB1_BASE_LO
regCP_IB1_BASE_HI
regCP_IB1_BUFSZ
regCP_MES_DEBUG_INTERRUPT_INSTR_PNTR

Above registers are part of the asic but not of
the offset file for gc_11_0_0_offset.h and hence
adding them.

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Sunil Khatri <sunil.khatri@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2024-05-23 15:13:34 -04:00
Li Ma
19f0edd897 drm/amdgpu/atomfirmware: add intergrated info v2.3 table 
[Why]
The vram width value is 0.
Because the integratedsysteminfo table in VBIOS has updated to 2.3.

[How]
Driver needs a new intergrated info v2.3 table too.
Then the vram width value will be correct.

Signed-off-by: Li Ma <li.ma@amd.com>
Reviewed-by: Yifan Zhang <yifan1.zhang@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2024-05-23 15:10:48 -04:00
Kenneth Feng
e7d1f1162b drm/amd/amdgpu: add thm 14.0.2 header file 
add thm 14.0.2 header file

v2: add license, update to latest changes (Alex)

Signed-off-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Likun Gao <Likun.Gao@amd.com>
 2024-05-20 16:20:26 -04:00
Asad Kamal
64af3d3d66 Revert "drm/amd/pm: Add gpu_metrics_v1_6" 
Remove gpu_metrics_v1_6 temporarily until tool support is ready

This reverts commit 00dedab07b.

Signed-off-by: Asad Kamal <asad.kamal@amd.com>
Reviewed-by: Lijo Lazar <lijo.lazar@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2024-05-20 16:20:26 -04:00
Lijo Lazar
83b90b138b drm/amd/pm: Add xgmi plpd policy to pm_policy 
Add support to set XGMI PLPD policy levels through 'pm_policy/xgmi_plpd'
sysfs node.

Signed-off-by: Lijo Lazar <lijo.lazar@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Asad Kamal <asad.kamal@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2024-05-17 17:40:39 -04:00
Lijo Lazar
4d154b1ca5 drm/amd/pm: Add support for DPM policies 
Add support to set/get information about different DPM policies. The
support is only available on SOCs which use swsmu architecture.

A DPM policy type may be defined with different levels. For example, a
policy may be defined to select Pstate preference and then later a
pstate preference may be chosen.

Signed-off-by: Lijo Lazar <lijo.lazar@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Asad Kamal <asad.kamal@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2024-05-17 17:40:38 -04:00
Lijo Lazar
8ce97959ec drm/amdgpu: Add nps info table to IP discovery 
Add support to fetch NPS info table in IP discovery table.

Signed-off-by: Lijo Lazar <lijo.lazar@amd.com>
Reviewed-by: Le Ma <le.ma@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2024-05-17 17:40:36 -04:00
Asad Kamal
00dedab07b drm/amd/pm: Add gpu_metrics_v1_6 
Add new gpu_metrics_v1_6 to acquire accumulated
throttler residencies

Signed-off-by: Asad Kamal <asad.kamal@amd.com>
Reviewed-by: Lijo Lazar <lijo.lazar@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2024-05-17 17:10:15 -04:00
shaoyunl
4488cd671c drm/amdgpu: enable unmapped doorbell handling basic mode on mes 12 
This reverts commit fcc5df722d.

Signed-off-by: shaoyunl <shaoyun.liu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2024-05-17 17:05:38 -04:00
Jack Xiao
ad5c0a79df drm/amdgpu/mes12: add legacy setting hw resource interface 
For unified mes fw, add the legacy interface to set hardware
resources.

v2: remove warning (Alex)

Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2024-05-02 16:18:14 -04:00
shaoyunl
fcc5df722d drm/amdgpu: Disable unmapped doorbell handling basic mode on mes 12 
The new mechanism for unmapped doorbell handling requires both driver side and
MES fw side change. The FW side changes are still not released.

Signed-off-by: shaoyunl <shaoyun.liu@amd.com>
Reviewed-by: Harish Kasiviswanthan <Harish.Kasiviswanthan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2024-05-02 16:18:14 -04:00
David Belanger
48f0bdf4e3 drm/amdkfd: Added MQD manager files for GFX12. 
Initial implementation, based on GFX11.

v2: Removed dbg_wa code as not needed on GFX12.
v3: squash in SDMA queue fixes (Alex)
v4: rebase (Alex)

Signed-off-by: David Belanger <david.belanger@amd.com>
Reviewed-by: Harish Kasiviswanathan <Harish.Kasiviswanathan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2024-05-02 16:18:12 -04:00
shaoyunl
19e69a5d28 drm/amdgpu: Enable unmapped doorbell handling basic mode on mes 12 
Enable basic mode handling for doorbell ring on unmapped CP queue.
In this mode, MES can start schedule the queue mapping based on HW
interrupt instead of timer.

Signed-off-by: shaoyunl <shaoyun.liu@amd.com>
Reviewed-by: Harish Kasiviswanthan <Harish.Kasiviswanthan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2024-05-02 16:18:12 -04:00
Harish Kasiviswanathan
415fcb8c50 drm/amdgpu: Add mes_v12_api_def.h for gfx12 
Add MES_v12 header definition for gfx12

v2: Modify SET_SHADER_DEBUGGER to match mes_v11 definition. This doesn't
change the structure layout

v3: Removed unncessary comment and spaces

Signed-off-by: Harish Kasiviswanathan <Harish.Kasiviswanathan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2024-05-02 16:18:10 -04:00
Likun Gao
d34420f203 drm/amdgpu: add gfx12 mqd structures 
memory queue descriptors for gfx12.

v2: squash in sdma updates (Alex)

Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2024-04-30 10:01:44 -04:00
Sunil Khatri
fbbbf6fb3f drm/amdgpu: add function descripion of new functions 
Add function description of the new functions added
in amd_ip_funcs.

new functions added are:
a. dump_ip_state
b. print_ip_state

Signed-off-by: Sunil Khatri <sunil.khatri@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2024-04-30 09:57:58 -04:00
Hawking Zhang
3a99045c56 drm/amdgpu: Add mmhub v4_1_0 ip headers (v4) 
v1: Add mmhub v4_1_0 register offset and shift masks
    header files. (Hawking)
v2: Update mmhub v4_1_0 register offset and shift masks
    header files to RE2. (Likun)
v3: Update mmhub v4_1_0 register offset and shift masks
    header files to RE2.5 (Likun)
v4: Clean up mmhub v4_1_0 ip headers (Alex)

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2024-04-30 09:51:27 -04:00
Hawking Zhang
ec426766a4 drm/amdgpu: Add soc24 chip enum definitions (v4) 
Add enum definitions for soc24.

v2: Updates (Alex)
v3: Updates (Alex)
v4: Fix clash with display code (Alex)

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2024-04-30 09:46:34 -04:00
Hawking Zhang
db4f0d544e drm/amdgpu: Add gc v12_0_0 ip headers (v4) 
v1: Add gc v12_0_0 register offset and shift masks
    header files. (Hawking)
v2: Update gc v12_0_0 register offset and shift masks
    header files to LSD version. (Likun)
v3: Update gc v12_0_0 register offset and shift masks
    header files to RE3 version. (Likun)
v4: Updates (Alex)
v5: updates (Alex)

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2024-04-30 09:46:29 -04:00
Aurabindo Pillai
59a0c03a50 drm/amd: Add DCN401 related register definitions 
Update register headers.

Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Acked-by: Rodrigo Siqueira <rodrigo.siqueira@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2024-04-26 17:23:08 -04:00
Jack Xiao
4b515127e8 drm/amdgpu/mes11: update ADD_QUEUE interface 
Update ADD_QUEUE interface for mes11 to support
mes mapping legacy queue.

Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2024-04-26 17:22:45 -04:00
Rodrigo Siqueira
5e66f6eaa2 drm/amd/display: Add some missing HDMI registers for DCN3x 
This commit add some missing HDMI control registers to DCN3x.

Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2024-04-26 17:22:42 -04:00
Rodrigo Siqueira
71dfa617ea drm/amd/display: Add missing debug registers for DCN2/3/3.1 
This commit add some missing debug registers for DPCS and RDPC debug.

Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2024-04-26 17:22:40 -04:00
Sunil Khatri
40356542c3 drm/amdgpu: add protype for print ip state 
Add the protoype for print ip state to be used
to print the registers in devcoredump during
a gpu reset.

Signed-off-by: Sunil Khatri <sunil.khatri@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2024-04-26 17:22:39 -04:00
Sunil Khatri
c395dbb68b drm/amdgpu: add support of gfx10 register dump 
Adding gfx10 gc registers to be used for register
dump via devcoredump during a gpu reset.

Signed-off-by: Sunil Khatri <sunil.khatri@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2024-04-26 17:22:39 -04:00
Sunil Khatri
e21d253bd7 drm/amdgpu: add prototype for ip dump 
Add the prototype to dump ip registers
for all ips of different asics and set
them to NULL for now. Based on the
requirement add a function pointer for
each of them.

Signed-off-by: Sunil Khatri <sunil.khatri@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2024-04-26 17:22:39 -04:00
Sunil Khatri
cba9b630f0 drm/amdgpu: add IH_RING1_CFG headers for IH v6.0 
Add offsets, mask and shift macros for IH v6.0
which are needed to configure ring1 client irq
redirection.

Signed-off-by: Sunil Khatri <sunil.khatri@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2024-04-18 23:46:31 -04:00
chongli2
f6ac084236 drm/amd/amdgpu: support MES command SET_HW_RESOURCE1 in sriov 
support MES command SET_HW_RESOURCE1 in sriov

Signed-off-by: chongli2 <chongli2@amd.com>
Reviewed-by: Jingwen Chen <Jingwen.Chen2@amd.com>
Acked-by: Jingwen Chen <Jingwen.Chen2@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2024-04-09 22:08:53 -04:00
Ma Jun
b2207dc698 drm/amdgpu/pm: Add support for MACO flag checking 
Add support for MACO flag checking.
MACO mode only works if BACO is supported.

Signed-off-by: Ma Jun <Jun.Ma2@amd.com>
Reviewed-by: Lijo Lazar <lijo.lazar@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2024-04-09 22:07:59 -04:00
Rodrigo Siqueira
be239684b1 drm/amd/display: Add missing registers 
Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Acked-by: Roman Li <roman.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2024-04-09 22:06:16 -04:00
Rodrigo Siqueira
e7927b2914 drm/amd/display: Add some missing debug registers 
Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Acked-by: Roman Li <roman.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2024-04-09 22:05:50 -04:00
Lang Yu
f3e698978c drm/amdgpu/umsch: update UMSCH 4.0 FW interface 
Align with FW changes.

Signed-off-by: Lang Yu <Lang.Yu@amd.com>
Reviewed-by: Veerabadhran Gopalakrishnan <Veerabadhran.Gopalakrishnan@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2024-03-27 01:44:07 -04:00
Hawking Zhang
c9d7f802e6 drm/amdgpu: Add smuio v14_0_2 ip headers (v4) 
v1: Add smuio v14_0_2 register offset and shift masks
    header files. (Hawking)
v2: Update smuio v14_0_2 register offset and shift masks
    header files to RE2. (Likun)
v3: Update smuio v14_0_2 register offset and shift masks
    header files to RE2.5. (Likun)
v4: Clean up smuio v14_0_2 ip headers (Alex)

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2024-03-20 13:38:16 -04:00
Rodrigo Siqueira
0ba7ad7e42 drm/amd/display: Add missing registers and offset 
[Why & How]
Registers and offset are missing. Add it back

Acked-by: Wayne Lin <wayne.lin@amd.com>
Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2024-03-20 13:38:13 -04:00
Xiaojian Du
d1b2703cc2 drm/amdgpu: add the sensor value of VCN activity 
This will add the sensor value of VCN activity for some ASICs.

Signed-off-by: Xiaojian Du <Xiaojian.Du@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2024-03-20 13:37:37 -04:00
Tao Zhou
b7b23877a2 drm/amdgpu: add new bit definitions for GC 9.0 PROTECTION_FAULT_STATUS 
Add UCE and FED bit definitions.

Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2024-03-20 13:37:36 -04:00
Hawking Zhang
b9e9b8eaaf drm/amdgpu: Add pcie v6_1_0 ip headers (v5) 
v1: Add pcie v6_1_0 register offset and shift masks
    header files. (Hawking)
v2: Update pcie v6_1_0 register offset and shift masks
    header files to RE2. (Likun)
v3: Update pcie v6_1_0 register offset and shift masks
    header files to RE2.5. (Likun)
v4: Update pcie v6_1_0 register offset and shift masks
    header files to RE3. (Likun)
v5: Updates (Alex)

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2024-03-07 15:32:38 -05:00
Hawking Zhang
d9b772420f drm/amdgpu: Add nbif v6_3_1 ip headers (v5) 
v1: Add nbif v6_3_1 register offset and shift masks
    header files. (Hawking)
v2: Update nbif v6_3_1 register offset and shift masks
    header files to RE2. (Likun)
v3: Update nbif v6_3_1 register offset and shift masks
    header files to RE2.5. (Likun)
v4: Update nbif v6_3_1 register offset and shift masks
    header files to RE3. (Likun)
v5: Updates (Alex)

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2024-03-07 15:32:31 -05:00
Hamza Mahfooz
3a80fe500e drm/amd: add register headers for DCN351 
Add register headers for DCN 3.5.1.

Signed-off-by: Hamza Mahfooz <hamza.mahfooz@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2024-03-04 15:59:07 -05:00
Aurabindo Pillai
47136be638 drm/amd: Update atomfirmware.h for DCN401 
Add new firmware header definitions reqiured for DCN401

Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2024-02-22 10:26:32 -05:00