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7460 Commits

Author SHA1 Message Date
Ville Syrjälä
00efddc608 drm/i915/vga: Extract intel_vga_regs.h 
Extract the VGACNTR register definitions into their own
header file, to declutter i915_reg.h a bit.

v2: Group the register offst definitions together (Jani)

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20250417114454.12836-4-ville.syrjala@linux.intel.com
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
 2025-04-25 18:48:01 +03:00
Animesh Manna
93d33af699 drm/i915/display: Disintegrate sink alpm enable from psr with lobf 
Make a generic alpm enable function for sink which can be used for
PSR2/PR/Lobf.

v1: Initial version.
v2: Move code comment to intel_psr_needs_alpm(). [Jouni]

Signed-off-by: Animesh Manna <animesh.manna@intel.com>
Reviewed-by: Jouni Högander <jouni.hogander@intel.com>
Link: https://lore.kernel.org/r/20250423092334.2294483-12-animesh.manna@intel.com
 2025-04-24 13:55:17 +05:30
Animesh Manna
554698b826 drm/i915/alpm: Add intel_psr_need_alpm() to simplify alpm check 
Simplify the alpm check which will be used multiple places like
source configuration, sink enablement etc.

Signed-off-by: Animesh Manna <animesh.manna@intel.com>
Reviewed-by: Jouni Högander <jouni.hogander@intel.com>
Link: https://lore.kernel.org/r/20250423092334.2294483-11-animesh.manna@intel.com
 2025-04-24 13:55:08 +05:30
Animesh Manna
2063174c22 drm/i915/lobf: Check for sink error and disable LOBF 
Disable LOBF/ALPM for any erroneous condition from sink side.

v1: Initial version.
v2: Add centralized alpm error handling. [Jouni]
v3: Improve debug print. [Jouni]
v4: Disable alpm permanently for sink error. [Jouni]

Signed-off-by: Animesh Manna <animesh.manna@intel.com>
Reviewed-by: Jouni Högander <jouni.hogander@intel.com>
Link: https://lore.kernel.org/r/20250423092334.2294483-10-animesh.manna@intel.com
 2025-04-24 13:55:01 +05:30
Animesh Manna
acff6d6bde drm/i915/lobf: Add mutex for alpm update 
The ALPM_CTL can be updated from different context, so
add mutex to sychonize the update.

Signed-off-by: Animesh Manna <animesh.manna@intel.com>
Reviewed-by: Jouni Högander <jouni.hogander@intel.com>
Link: https://lore.kernel.org/r/20250423092334.2294483-9-animesh.manna@intel.com
 2025-04-24 13:54:57 +05:30
Animesh Manna
917abe4bc7 drm/i915/lobf: Add debug interface for lobf 
Add an interface in debugfs which will help in debugging LOBF
feature.

v1: Initial version.
v2:
- Remove FORCE_EN flag. [Jouni]
- Change prefix from I915 to INTEL. [Jani]
- Use u8 instead of bool for lobf-debug flag. [Jani]
v3:
- Use intel_connector instead of display. [Jani]
- Remove edp connector check as it was already present
in caller function. [Jani]
- Remove loop of searching edp encoder which is directly
accessible from intel_connector. [Jani]
v4:
- Simplify alpm debug to bool instead of bit-mask. [Jani]
v5:
- Remove READ_ONCE(). [Jani]
- Modify variable name to *_disable_*. [Jouni]
v6: Improved debug print. [Jouni]

Signed-off-by: Animesh Manna <animesh.manna@intel.com>
Reviewed-by: Jouni Högander <jouni.hogander@intel.com>
Link: https://lore.kernel.org/r/20250423092334.2294483-8-animesh.manna@intel.com
 2025-04-24 13:54:51 +05:30
Animesh Manna
64a5dd770d drm/i915/lobf: Update lobf if any change in dependent parameters 
For every commit the dependent condition for LOBF is checked
and accordingly update has_lobf flag which will be used
to update the ALPM_CTL register during commit.

v1: Initial version.
v2: Avoid reading h/w register without has_lobf check. [Jani]
v3: Update LOBF in post plane update instead of separate function. [Jouni]
v4:
- Add lobf disable print. [Jouni]
- Simplify condition check for enabling/disabling lobf. [Jouni]
v5: Disable LOBF in pre_plane_update(). [Jouni]
v6: use lobf flag of old_crtc_state and write 0 into ALPM_CTL. [Jouni]

Signed-off-by: Animesh Manna <animesh.manna@intel.com>
Reviewed-by: Jouni Högander <jouni.hogander@intel.com>
Link: https://lore.kernel.org/r/20250423092334.2294483-7-animesh.manna@intel.com
 2025-04-24 13:54:46 +05:30
Animesh Manna
2c809080d2 drm/i915/lobf: Add fixed refresh rate check in compute_config() 
LOBF can be enabled with vrr fixed rate mode, so add check
if vmin = vmax = flipline in compute_config().

Signed-off-by: Animesh Manna <animesh.manna@intel.com>
Reviewed-by: Jouni Högander <jouni.hogander@intel.com>
Link: https://lore.kernel.org/r/20250423092334.2294483-6-animesh.manna@intel.com
 2025-04-24 13:54:41 +05:30
Animesh Manna
504766382e drm/i915/lobf: Disintegrate alpm_disable from psr_disable 
Currently clearing of alpm registers is done through psr_disable()
which is always not correct, without psr also alpm can exist. So
dis-integrate alpm_disable() from psr_disable().

v1: Initial version.
v2:
- Remove h/w register read from alpm_disable(). [Jani]

Signed-off-by: Animesh Manna <animesh.manna@intel.com>
Reviewed-by: Jouni Högander <jouni.hogander@intel.com>
Link: https://lore.kernel.org/r/20250423092334.2294483-5-animesh.manna@intel.com
 2025-04-24 13:54:36 +05:30
Animesh Manna
ad89a60d51 drm/i915/lobf: Add debug print for LOBF 
Lobf is enabled part of ALPM configuration and if has_lobf
is set to true respective bit for LOBF will be set. Add debug
print while setting the bitfield of LOBF.

Signed-off-by: Animesh Manna <animesh.manna@intel.com>
Reviewed-by: Jouni Högander <jouni.hogander@intel.com>
Link: https://lore.kernel.org/r/20250423092334.2294483-4-animesh.manna@intel.com
 2025-04-24 13:54:29 +05:30
Animesh Manna
172757acd6 drm/i915/lobf: Add lobf enablement in post plane update 
Enablement of LOBF is added in post plane update whenever
has_lobf flag is set. As LOBF can be enabled in non-psr
case as well so adding in post plane update. There is no
change of configuring alpm with psr path.

v1: Initial version.
v2: Use encoder-mask to find the associated encoder from
crtc-state. [Jani]
v3: Remove alpm_configure from intel_psr.c. [Jouni]

Signed-off-by: Animesh Manna <animesh.manna@intel.com>
Reviewed-by: Jouni Högander <jouni.hogander@intel.com>
Link: https://lore.kernel.org/r/20250423092334.2294483-3-animesh.manna@intel.com
 2025-04-24 13:54:24 +05:30
Jouni Högander
278a7be9b8 drm/i915/alpm: use variable from intel_crtc_state instead of intel_psr 
Currently code is making assumption that PSR is enabled when
intel_alpm_configure is called. This doesn't work if alpm is configured
before PSR is enabled.

Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
Reviewed-by: Animesh Manna <animesh.manna@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
Link: https://lore.kernel.org/r/20250423092334.2294483-2-animesh.manna@intel.com
 2025-04-24 13:53:34 +05:30
Jani Nikula
1503bab749 drm/i915/reg: use REG_BIT and friends to define DP registers 
Define the DP register contents using the REG_BIT, REG_GENMASK,
etc. macros. Ditch the unhelpful comments. Rename eDP related register
content macros to have EDP_ prefix.

Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
Link: https://lore.kernel.org/r/20250423100213.720585-1-jani.nikula@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
 2025-04-24 10:33:52 +03:00
Jouni Högander
4332473e7c drm/i915/display: Rename vblank DC workaround functions and variables 
We have extended using vblank DC workaround mechanism for
Wa_16025596647. Rename related functions and variables:

vblank_wa_num_pipes -> vblank_enable_count
vblank_dc_work -> vblank_notify_work
intel_display_vblank_dc_work -> intel_display_vblank_notify_work

Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
Reviewed-by: Mika Kahola <mika.kahola@intel.com>
Link: https://lore.kernel.org/r/20250414100508.1208774-14-jouni.hogander@intel.com
 2025-04-23 12:16:34 +03:00
Jouni Högander
9df7215f4b drm/i915/display: Rename intel_psr_needs_block_dc_vblank 
Scope of intel_psr_needs_block_dc_vblank has changed now. Rename it as
intel_psr_needs_vblank_notification. Also rename
intel_crtc::block_dc_for_vblank as intel_crtc:vblank_psr_notify

Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
Reviewed-by: Mika Kahola <mika.kahola@intel.com>
Link: https://lore.kernel.org/r/20250414100508.1208774-13-jouni.hogander@intel.com
 2025-04-23 12:16:33 +03:00
Jouni Högander
39e4d3c2f8 drm/i915/psr: Apply underrun on PSR idle workaround 
This patch is applying workaround for underrun on idle PSR HW issue
(Wa_16025596647) when PSR is getting enabled. It uses vblank enable/disable
status, DC5/6 enabled disabled and enabled pipes count information made
available.

This patch is also adding calls to dc5/dc6, vblank enable/disable and pipe
enable/disable notification functions as needed.
intel_psr_needs_block_dc_vblank is modified to get vblank enable/disable
notification on PSR capable system.

v2: use intel_dmc interface instead of directly writing dmc register

Bspec: 74151
Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
Reviewed-by: Mika Kahola <mika.kahola@intel.com>
Link: https://lore.kernel.org/r/20250414100508.1208774-12-jouni.hogander@intel.com
 2025-04-23 12:16:31 +03:00
Jouni Högander
2978eb1841 drm/i915/dmc: Add interface to control start of PKG C-state exit 
Add interface to control if package C exit starts at the start of the
undelayed vblank. This is needed to implement workaround for underrun on
idle PSR HW issue (Wa_16025596647).

Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
Reviewed-by: Mika Kahola <mika.kahola@intel.com>
Link: https://lore.kernel.org/r/20250414100508.1208774-11-jouni.hogander@intel.com
 2025-04-23 12:16:31 +03:00
Jouni Högander
0c427ac78a drm/i915/psr: Add interface to notify PSR of vblank enable/disable 
To implement Wa_16025596647 we need to get notification of vblank interrupt
enable/disable. Add new interface to PSR code for this notification.

Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
Reviewed-by: Mika Kahola <mika.kahola@intel.com>
Link: https://lore.kernel.org/r/20250414100508.1208774-10-jouni.hogander@intel.com
 2025-04-23 12:16:30 +03:00
Jouni Högander
b7effa3238 drm/i915/psr: Add mechanism to notify PSR of DC5/6 enable disable 
We need to apply/remove workaround for underrun on idle PSR HW issue
(Wa_16025596647) when DC5/6 is enabled/disabled. This patch implements
mechanism to notify PSR about DC5/6 enable/disable and applies/removes the
workaround using this notification.

Bspec: 74115

Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
Reviewed-by: Mika Kahola <mika.kahola@intel.com>
Link: https://lore.kernel.org/r/20250414100508.1208774-9-jouni.hogander@intel.com
 2025-04-23 12:16:29 +03:00
Jouni Högander
f02658c46c drm/i915/psr: Add mechanism to notify PSR of pipe enable/disable 
We need to apply/remove workaround for underrun on idle PSR HW issue
(Wa_16025596647) when new pipe is enabled or pipe is getting disabled. This
patch implements mechanism to notify PSR about pipe enable/disable and
applies/removes the workaround using this notification.

Bspec: 74151

Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
Reviewed-by: Mika Kahola <mika.kahola@intel.com>
Link: https://lore.kernel.org/r/20250414100508.1208774-8-jouni.hogander@intel.com
 2025-04-23 12:16:28 +03:00
Jouni Högander
0de99007c7 drm/i915/psr: Block PKG C-State when enabling PSR 
Block PKG C-State when enabling PSR when enabling PSR as described in
workaround for underrun on idle PSR HW issue (Wa_16025596647).

v2: use intel_dmc_block_pkgc instead of directly writing dmc register

Bspec: 74151
Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
Reviewed-by: Mika Kahola <mika.kahola@intel.com>
Link: https://lore.kernel.org/r/20250414100508.1208774-7-jouni.hogander@intel.com
 2025-04-23 12:16:28 +03:00
Jouni Högander
973deeada0 drm/i915/dmc: Add interface to block PKG C-state 
Add interface to block PKG C-state. This is needed to implement workaround
for underrun on idle PSR HW issue (Wa_16025596647).

Bspec: 74151
Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
Reviewed-by: Mika Kahola <mika.kahola@intel.com>
Link: https://lore.kernel.org/r/20250414100508.1208774-6-jouni.hogander@intel.com
 2025-04-23 12:16:27 +03:00
Jouni Högander
f991ef47da drm/i915/dmc: Add PIPEDMC_BLOCK_PKGC_SW definitions 
We need PIPEDMC_BLOCK_PKGC_SW definitions to implement workaround for
underrun on idle PSR HW issue (Wa_16025596647). Add PIPEDMC_BLOCK_PKGC_SW
register definitions.

Bspec: 71265

Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
Reviewed-by: Mika Kahola <mika.kahola@intel.com>
Link: https://lore.kernel.org/r/20250414100508.1208774-5-jouni.hogander@intel.com
 2025-04-23 12:16:26 +03:00
Jouni Högander
b23c157d46 drm/i915/dmc: Add PIPEDMC_EVT_CTL register definition 
To implement workaround for underrun on idle PSR HW issue (Wa_16025596647)
we need PIPEDMC_EVT_CTL_4 register. Add PIPEDMC_EVT_CTL_4 register
definitions.

Bspec: 67576

Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
Reviewed-by: Mika Kahola <mika.kahola@intel.com>
Link: https://lore.kernel.org/r/20250414100508.1208774-4-jouni.hogander@intel.com
 2025-04-23 12:16:26 +03:00
Jouni Högander
a99b050ca7 drm/i915/psr: Store enabled non-psr pipes into intel_crtc_state 
To implement workaround for underrun on idle PSR HW issue (Wa_16025596647)
we need to know enabled. Figure out which non-PSR pipes we will have active
and store it into intel_crtc_state->active_non_psr_pipes. This is currently
assuming only one eDP on a time. I.e. possible secondary eDP with PSR
capable panel is not considered.

Bspec: 74151

Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
Reviewed-by: Mika Kahola <mika.kahola@intel.com>
Link: https://lore.kernel.org/r/20250414100508.1208774-3-jouni.hogander@intel.com
 2025-04-23 12:16:25 +03:00
Jouni Högander
208b22a86f drm/i915/display: Add new interface for getting dc_state 
To implement workaround for underrun on idle PSR HW issue (Wa_16025596647)
we need to have current configured DC state available. Add new interface
for this purpose.

Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
Reviewed-by: Mika Kahola <mika.kahola@intel.com>
Link: https://lore.kernel.org/r/20250414100508.1208774-2-jouni.hogander@intel.com
 2025-04-23 12:16:24 +03:00
Jani Nikula
246b259f1d drm/i915/pch: abstract fake PCH detection better 
Abstract detection of platforms with south display on the same PCI
device or SoC die as north display, and all around clarify what this
means. Debug log about it for good measure.

Reviewed-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
Link: https://lore.kernel.org/r/95cd619b63a81a0a7f8c73a64694da9d41e3a575.1744880985.git.jani.nikula@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
 2025-04-22 15:46:29 +03:00
Jani Nikula
2958620abc drm/i915/display: drop lots of unnecessary #include i915_drv.h 
With the PCH macros switched to use struct intel_display, we have a
number of files that no longer need struct drm_i915_private or anything
else from i915_drv.h anymore. Remove the #include, and add the missing
includes that were previously implicit.

v2: Drop even more of the includes

Reviewed-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
Link: https://lore.kernel.org/r/5dc9e6a98461c344febac4c645875d8688eba906.1744880985.git.jani.nikula@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
 2025-04-22 15:46:29 +03:00
Jani Nikula
4e9b0ac17f drm/i915/display: pass struct intel_display to PCH macros 
Now that INTEL_PCH_TYPE() and HAS_PCH_*() macros are under display, and
accept a struct intel_display pointer, use that instead of struct
drm_i915_private pointer in display code.

This is done naively by running:

$ sed -i 's/\(INTEL_PCH_TYPE\|HAS_PCH_[A-Z0-9_-]*\)([^)]*)/\1(display)/g' \
  $(find drivers/gpu/drm/i915/display -name "*.c")

and fixing the fallout, i.e. removing unused local i915 variables and
adding display variables where needed.

v2: Rebase

Reviewed-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
Link: https://lore.kernel.org/r/999f4d7b8ed11739b1c5ec8d6408fc39d5e3776b.1744880985.git.jani.nikula@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
 2025-04-22 15:46:29 +03:00
Jani Nikula
a8c2c8d329 drm/i915/audio: don't set LPE audio irq chip data, it's unused 
Nobody uses the irq chip data. Stop setting it, and as a bonus get rid
of another struct drm_i915_private * reference.

Reviewed-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
Link: https://lore.kernel.org/r/d75ec986093c912de67a42782aa5a49357a9f8e5.1744222449.git.jani.nikula@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
 2025-04-17 11:31:13 +03:00
Jani Nikula
69cb72d393 drm/i915/display: switch to display->platform.dgfx from IS_DGFX() 
Prefer display->platform.dgfx based platform detection over the old
IS_DGFX() macro.

Reviewed-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
Link: https://lore.kernel.org/r/99de7f8f26156afbddcdac850088e6a96d322c55.1744222449.git.jani.nikula@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
 2025-04-17 11:31:13 +03:00
Jani Nikula
4a3506d174 drm/i915/hdmi: switch to display->platform based platform detection 
Prefer display->platform based platform detection over the old IS_*()
macros.

Reviewed-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
Link: https://lore.kernel.org/r/02659f1144180f328167734f7e31499833749c8d.1744222449.git.jani.nikula@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
 2025-04-17 11:31:13 +03:00
Jani Nikula
1058ee1b20 drm/i915/gmbus: switch to display->platform based platform detection 
Prefer display->platform based platform detection over the old IS_*()
macros.

Reviewed-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
Link: https://lore.kernel.org/r/7a69d2ffa15306da899b98e0d6af09b4df1b7ec3.1744222449.git.jani.nikula@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
 2025-04-17 11:31:13 +03:00
Jani Nikula
5739a143db drm/i915/dpio: switch to display->platform based platform detection 
Prefer display->platform based platform detection over the old IS_*()
macros.

Reviewed-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
Link: https://lore.kernel.org/r/36166cd0cfdb88df4c0322c4edea69fad5ad7177.1744222449.git.jani.nikula@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
 2025-04-17 11:31:13 +03:00
Jani Nikula
af6fe09131 drm/i915/dp-aux: switch to display->platform based platform detection 
Prefer display->platform based platform detection over the old IS_*()
macros.

Reviewed-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
Link: https://lore.kernel.org/r/a5cde717001eb2843344beb21ca8907ab2e43d4f.1744222449.git.jani.nikula@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
 2025-04-17 11:31:13 +03:00
Jani Nikula
d42652314c drm/i915/dmc: switch to display->platform based platform detection 
Prefer display->platform based platform detection over the old IS_*()
macros.

Reviewed-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
Link: https://lore.kernel.org/r/eda2b6cd285ec76d57d91ea3fe33158852aaec22.1744222449.git.jani.nikula@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
 2025-04-17 11:31:13 +03:00
Jani Nikula
56bcacebad drm/i915/crt: switch to display->platform based platform detection 
Prefer display->platform based platform detection over the old IS_*()
macros.

Reviewed-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
Link: https://lore.kernel.org/r/83980c1ae53157ef5d65d7ce99b294889622faa8.1744222449.git.jani.nikula@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
 2025-04-17 11:31:13 +03:00
Jani Nikula
d358cee747 drm/i915/frontbuffer: convert intel_frontbuffer.[ch] to struct intel_display 
Going forward, struct intel_display is the main display device data
pointer. Convert intel_frontbuffer.[ch] to struct intel_display.

Reviewed-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
Link: https://lore.kernel.org/r/ef0860583b7d6ad141959f84c25657e0c102d6d2.1744222449.git.jani.nikula@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
 2025-04-17 11:31:13 +03:00
Jani Nikula
c370285b81 drm/i915/sprite: convert intel_sprite_uapi.c to struct intel_display 
Going forward, struct intel_display is the main display device data
pointer. Convert intel_sprite_uapi.c to struct intel_display.

Reviewed-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
Link: https://lore.kernel.org/r/d4f71c2976a1a28b4e74c2fc1097090fe7f78743.1744222449.git.jani.nikula@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
 2025-04-17 11:31:12 +03:00
Jani Nikula
46b5871865 drm/i915/display: convert intel_modeset_verify.c to struct intel_display 
Going forward, struct intel_display is the main display device data
pointer. Convert intel_modeset_verify.[ch] to struct intel_display.

Reviewed-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
Link: https://lore.kernel.org/r/b01a3ef3dbb2ffdaa6b5e9ebec14f91efcca3049.1744222449.git.jani.nikula@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
 2025-04-17 11:31:12 +03:00
Jani Nikula
c4f9a886ee drm/i915/display: convert intel_modeset_setup.[ch] to struct intel_display 
Going forward, struct intel_display is the main display device data
pointer. Convert intel_modeset_setup.[ch] to struct intel_display.

Reviewed-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
Link: https://lore.kernel.org/r/21d51387a36f027313a0687d09a14586eb8f71a6.1744222449.git.jani.nikula@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
 2025-04-17 11:31:12 +03:00
Jani Nikula
8dcb54d440 drm/i915/fb: convert intel_fbdev.[ch] and intel_fbdev_fb.[ch] to struct intel_display 
Going forward, struct intel_display is the main display device data
pointer. Convert intel_fbdev.[ch] and as much as possible of
intel_fbdev_fb.[ch] to struct intel_display.

Reviewed-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
Link: https://lore.kernel.org/r/49651754f3716041f97984e47c15d331851870a5.1744222449.git.jani.nikula@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
 2025-04-17 11:31:12 +03:00
Jani Nikula
27dbba9f54 drm/i915/irq: convert ibx_irq_reset() into ibx_display_irq_reset() 
Observe that ibx_irq_reset() is really ibx_display_irq_reset(). Make it
so. Move to display, and call it directly from gen8_display_irq_reset()
instead of gen8_irq_reset().

Remove a nearby ancient stale comment while at it.

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://lore.kernel.org/r/20250409184702.3790548-1-jani.nikula@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
 2025-04-15 16:31:51 +03:00
Thomas Zimmermann
e12b34c571 Merge drm/drm-next into drm-misc-next 
Backmerging to get fixes from v6.15-rc2 into drm-misc-next.

Signed-off-by: Thomas Zimmermann <tzimmermann@suse.de>
 2025-04-15 13:12:02 +02:00
Khaled Almahallawy
0e96a9b947 drm/i915/display: Add link rate and lane count to i915_display_info 
Adding link rate and lane count information to i915_display_info makes it
easier and faster to access this data compared to checking kernel logs.
This is particularly beneficial for individuals who are not familiar with
i915 in the following scenarios:

* Debugging DP tunnel bandwidth usage in the Thunderbolt driver.
* During USB4 certification, it is necessary to know the link rate used by
  the monitor to prove that the DP tunnel can handle required rates.
* In PHY CTS, when the connector probes are not mounted correctly,
  some display lanes may not appear in the DP Oscilloscope, leading to CTS
  failures.

This change provides validation teams with an easy way to identify and
troubleshoot issues.

v2: separate seq_printf line (Jani)
v3: separate output line (Jani)

Cc: Imre Deak <imre.deak@intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Khaled Almahallawy <khaled.almahallawy@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Link: https://lore.kernel.org/r/20250409230214.963999-1-khaled.almahallawy@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
 2025-04-15 11:07:18 +03:00
Ankit Nautiyal
3a47280b76 drm/i915/dp: Check for HAS_DSC_3ENGINES while configuring DSC slices 
DSC 12 slices configuration is used for some specific cases with
Ultrajoiner. This can be supported only when each of the 4 joined pipes
have 3 DSC engines each.

Add the missing check for 3 DSC engines support before using 3 DSC
slices per pipe.

Fixes: be7f5fcdf4 ("drm/i915/dp: Enable 3 DSC engines for 12 slices")
Cc: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Cc: Suraj Kandpal <suraj.kandpal@intel.com>
Cc: <stable@vger.kernel.org> # v6.14+
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
Link: https://lore.kernel.org/r/20250414024256.2782702-3-ankit.k.nautiyal@intel.com
(cherry picked from commit da9b1c61e7)
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
 2025-04-15 10:33:37 +03:00
Ankit Nautiyal
ec0c7afa70 drm/i915/display: Add macro for checking 3 DSC engines 
3 DSC engines per pipe is currently supported only for BMG.
Add a macro to check whether a platform supports 3 DSC engines per pipe.

v2:Fix Typo in macro argument. (Suraj).
Added fixes tag.

Bspec: 50175
Fixes: be7f5fcdf4 ("drm/i915/dp: Enable 3 DSC engines for 12 slices")
Cc: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Cc: Suraj Kandpal <suraj.kandpal@intel.com>
Cc: <stable@vger.kernel.org> # v6.14+
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
Link: https://lore.kernel.org/r/20250414085701.2802374-1-ankit.k.nautiyal@intel.com
(cherry picked from commit 6998cfce0e)
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
 2025-04-15 10:33:30 +03:00
Ankit Nautiyal
da9b1c61e7 drm/i915/dp: Check for HAS_DSC_3ENGINES while configuring DSC slices 
DSC 12 slices configuration is used for some specific cases with
Ultrajoiner. This can be supported only when each of the 4 joined pipes
have 3 DSC engines each.

Add the missing check for 3 DSC engines support before using 3 DSC
slices per pipe.

Fixes: be7f5fcdf4 ("drm/i915/dp: Enable 3 DSC engines for 12 slices")
Cc: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Cc: Suraj Kandpal <suraj.kandpal@intel.com>
Cc: <stable@vger.kernel.org> # v6.14+
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
Link: https://lore.kernel.org/r/20250414024256.2782702-3-ankit.k.nautiyal@intel.com
 2025-04-15 11:14:26 +05:30
Ankit Nautiyal
6998cfce0e drm/i915/display: Add macro for checking 3 DSC engines 
3 DSC engines per pipe is currently supported only for BMG.
Add a macro to check whether a platform supports 3 DSC engines per pipe.

v2:Fix Typo in macro argument. (Suraj).
Added fixes tag.

Bspec: 50175
Fixes: be7f5fcdf4 ("drm/i915/dp: Enable 3 DSC engines for 12 slices")
Cc: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Cc: Suraj Kandpal <suraj.kandpal@intel.com>
Cc: <stable@vger.kernel.org> # v6.14+
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
Link: https://lore.kernel.org/r/20250414085701.2802374-1-ankit.k.nautiyal@intel.com
 2025-04-15 11:14:25 +05:30
Dave Airlie
b60301774a Merge tag 'drm-intel-next-2025-04-11' of https://gitlab.freedesktop.org/drm/i915/kernel into drm-next 
Cross-subsystem Changes:
- Update GVT MAINTAINERS (Jani)

Driver Changes:
- Updates for xe3lpd display (Gustavo)
- Fix link training interrupted by HPD pulse (Imre)
- Watermark bound checks for DSC (Ankit)
- VRR Refactor and other fixes and improvements (Ankit)
- More conversions towards intel_display struct (Gustavo, Jani)
- Other clean-up patches towards a display separation (Jani)
- Maintain asciibetical order for HAS_* macros (Ankit)
- Fixes around probe/initialization (Janusz)
- Fix build and doc build issue (Yue, Rodrigo)
- DSI related fixes (Suraj, William, Jani)
- Improve DC6 entry counter (Mohammed)
- Fix xe2hpd memory type identification (Vivek)
- PSR related fixes and improvements (Animesh, Jouni)
- DP MST related fixes and improvements (Imre)
- Fix scanline_offset for LNL+/BMG+ (Ville)
- Some gvt related fixes and changes (Ville, Jani)
- Some PLL code adjustment (Ville)
- Display wa addition (Vinod)
- DRAM type logging (Lucas)
- Pimp the initial FB readout (Ville)
- Some sagv/bw cleanup (Ville)
- Remove i915_display_capabilities debugfs entry (Jani)
- Move PCH type to display caps debugfs entry (Jani)

Signed-off-by: Dave Airlie <airlied@redhat.com>

From: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://lore.kernel.org/r/Z_kTqPX5Mjruq1pL@intel.com
 2025-04-15 05:06:51 +10:00