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27175 Commits

Author SHA1 Message Date
Christian König
a5492fe27f drm/amdgpu: fix amdgpu_cs_p1_user_fence 
The offset is just 32bits here so this can potentially overflow if
somebody specifies a large value. Instead reduce the size to calculate
the last possible offset.

The error handling path incorrectly drops the reference to the user
fence BO resulting in potential reference count underflow.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2023-08-31 16:39:28 -04:00
Evan Quan
90bcb9b595 drm/amdgpu: revise the device initialization sequences 
By placing the sysfs interfaces creation after `.late_int`. Since some
operations performed during `.late_init` may affect how the sysfs
interfaces should be created.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2023-08-31 16:35:33 -04:00
Evan Quan
3e38b634f9 drm/amd/pm: introduce a new set of OD interfaces 
There will be multiple interfaces(sysfs files) exposed with each representing
a single OD functionality. And all those interface will be arranged in a tree
liked hierarchy with the top dir as "gpu_od". Meanwhile all functionalities
for the same component will be arranged under the same directory.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2023-08-31 16:35:26 -04:00
Lang Yu
2cd1f65d31 drm/amdgpu: add UMSCH IP BLOCK TYPE definition 
Add IP BLOCK TYPE definition for Multimedia User Mode Scheduler
which is a hardware scheduler for VCN and VPE workload.

Signed-off-by: Lang Yu <Lang.Yu@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Veerabadhran Gopalakrishnan <Veerabadhran.Gopalakrishnan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2023-08-31 16:35:23 -04:00
Darren Powell
433c4dea31 amdgpu/pm: Optimize emit_clock_levels for arcturus - part 3 
split switch statement into two and consolidate the common
     code for printing most of the types of clock speeds

Signed-off-by: Darren Powell <darren.powell@amd.com>
Reviewed-by: Lijo Lazar <lijo.lazar@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2023-08-31 16:35:11 -04:00
Lang Yu
2c98de563b drm/amdgpu: add UMSCH 4.0 register headers 
Add headers for UMSCH 4.0.

v2: updates (Alex)

Signed-off-by: Lang Yu <Lang.Yu@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Veerabadhran Gopalakrishnan <Veerabadhran.Gopalakrishnan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2023-08-31 16:35:06 -04:00
Saleemkhan Jamadar
6be6e74b7d drm/amdgpu: enable PG flags for VCN 
Enable PG flags for VCN and Jpeg on IP 11_5_0

Signed-off-by: Saleemkhan Jamadar <saleemkhan.jamadar@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2023-08-31 16:35:02 -04:00
Saleemkhan Jamadar
844d8dd5b9 drm/amdgpu/discovery: add VCN 4.0.5 Support 
Enable VCN 4.0.5 on gc 11_5_0.

Signed-off-by: Saleemkhan Jamadar <saleemkhan.jamadar@amd.com>
Acked-by: Leo Liu <leo.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2023-08-31 16:34:58 -04:00
Saleemkhan Jamadar
c64f389506 drm/amdgpu/soc21: Add video cap query support for VCN_4_0_5 
Added the video capability query support for VCN version 4_0_5

Signed-off-by: Saleemkhan Jamadar <saleemkhan.jamadar@amd.com>
Reviewed-by: Veerabadhran Gopalakrishnan <Veerabadhran.Gopalakrishnan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2023-08-31 16:34:52 -04:00
Saleemkhan Jamadar
cc308acc9b drm/amdgpu:enable CG and PG flags for VCN 
Enable CG and PG flags for VCN on IP 11_5_0

Signed-off-by: Saleemkhan Jamadar <saleemkhan.jamadar@amd.com>
Acked-by: Leo Liu <leo.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2023-08-31 16:34:48 -04:00
Saleemkhan Jamadar
1827b37582 drm/amdgpu: add VCN_4_0_5 firmware support 
Add VCN_4_0_5 firmware support

Signed-off-by: Saleemkhan Jamadar <saleemkhan.jamadar@amd.com>
Acked-by: Leo Liu <leo.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2023-08-31 16:34:43 -04:00
Saleemkhan Jamadar
8f98a715da drm/amdgpu/jpeg: add jpeg support for VCN4_0_5 
Add jpeg support for VCN4_0_5

v2 - update license year (Leo Liu)

Signed-off-by: Saleemkhan Jamadar <saleemkhan.jamadar@amd.com>
Acked-by: Leo Liu <leo.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2023-08-31 16:34:36 -04:00
Saleemkhan Jamadar
547aad32ed drm/amdgpu: add VCN4 ip block support 
Add VCN 4.0.5 initialization and decoder/encoder ring functions.

v2 - update license year (Leo Liu)

Signed-off-by: Saleemkhan Jamadar <saleemkhan.jamadar@amd.com>
Acked-by: Leo Liu <leo.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2023-08-31 16:34:32 -04:00
Saleemkhan Jamadar
c2066c5fb3 drm/amdgpu: add vcn 4_0_5 header files 
Add VCN 4.0.5 registers

v2 - Add license header (Alexander Deucher)
v3 - updates (Alex)

Signed-off-by: Saleemkhan Jamadar <saleemkhan.jamadar@amd.com>
Acked-by: Leo Liu <leo.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2023-08-31 16:34:25 -04:00
Lang Yu
f9ecae9a4e drm/amdgpu: fix VPE front door loading issue 
Implement proper front door loading for vpe 6.1.

Signed-off-by: Lang Yu <Lang.Yu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2023-08-31 16:34:22 -04:00
Lang Yu
5f6e9cdc83 drm/amdgpu: add VPE FW version query support 
Add support to query VPE FW version.

Signed-off-by: Lang Yu <Lang.Yu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2023-08-31 16:34:19 -04:00
Lang Yu
3ee8fb7005 drm/amdgpu: enable VPE for VPE 6.1.0 
Enable Video Processing Engine on SoCs
that contain VPE 6.1.0.

Signed-off-by: Lang Yu <Lang.Yu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2023-08-31 16:34:16 -04:00
Lang Yu
523c12802d drm/amdgpu: add user space CS support for VPE 
Enable command submission to VPE from user space.

Signed-off-by: Lang Yu <Lang.Yu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2023-08-31 16:34:14 -04:00
Lang Yu
c5d67a0ec3 drm/amdgpu: add PSP loading support for VPE 
Add PSP loading support for Video Processing Engine.

Signed-off-by: Lang Yu <Lang.Yu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2023-08-31 16:34:10 -04:00
Lang Yu
9d4346bdbc drm/amdgpu: add VPE 6.1.0 support 
Add skeleton driver code. (Ray)
Add initial support for Video Processing Engine. (Lang)

Signed-off-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Lang Yu <Lang.Yu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2023-08-31 16:34:05 -04:00
Lang Yu
5861e47731 drm/amdgpu: add nbio 7.11 callback for VPE 
Add nbio callback to configure doorbell settings.

Signed-off-by: Lang Yu <Lang.Yu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2023-08-31 16:33:56 -04:00
Lang Yu
75fdd738ff drm/amdgpu: add nbio callback for VPE 
Add nbio callback to configure doorbell settings.

Signed-off-by: Lang Yu <Lang.Yu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2023-08-31 16:33:53 -04:00
Lang Yu
964a36d7a4 drm/amdgpu: add PSP FW TYPE for VPE 
Add PSP FW TYPE for Video Processing Engine.

Signed-off-by: Lang Yu <Lang.Yu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2023-08-31 16:33:50 -04:00
Lang Yu
4c63735fa8 drm/amdgpu: add UCODE ID for VPE 
Add UCODE ID for Video Processing Engine.

Signed-off-by: Lang Yu <Lang.Yu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2023-08-31 16:33:47 -04:00
Lang Yu
ce7b59c1e6 drm/amdgpu: add support for VPE firmware name decoding 
Add decoding VPE firmware name support.

Signed-off-by: Lang Yu <Lang.Yu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2023-08-31 16:33:43 -04:00
Lang Yu
2f3916bedb drm/amdgpu: add doorbell index for VPE 
Add doorbell index for Video Processing Engine.

Signed-off-by: Lang Yu <Lang.Yu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2023-08-31 16:33:40 -04:00
Lang Yu
130c470653 drm/amdgpu: add irq src id definitions for VPE 
The irq src id is used to route interrupts to
the corresponding handlers.

Signed-off-by: Lang Yu <Lang.Yu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2023-08-31 16:33:38 -04:00
Lang Yu
5e18361425 drm/amdgpu: add IH CLIENT ID for VPE 
Add Interrupt Handler Client ID for
Video Processing Engine.

Signed-off-by: Lang Yu <Lang.Yu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2023-08-31 16:33:35 -04:00
Lang Yu
0b233357a6 drm/amdgpu: add HWID for VPE 
Add HWID for Video Processing Engine.

Signed-off-by: Lang Yu <Lang.Yu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2023-08-31 16:33:31 -04:00
Lang Yu
b0fa855cab drm/amdgpu: add VPE firmware interface 
Add initial firmware interface. (Ray)
Add more opcodes and rename to vpe_v6_1. (Lang)

v2: Update copyright date (Alex)

Signed-off-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Lang Yu <Lang.Yu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2023-08-31 16:33:27 -04:00
Lang Yu
878fe05116 drm/amdgpu: add VPE firmware header definition 
Add firmware header definition for Video Processing Engine.

Signed-off-by: Lang Yu <Lang.Yu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2023-08-31 16:33:25 -04:00
Huang Rui
5b28f1c720 drm/amdgpu: add VPE HW IP BLOCK definition 
Add HW IP BLOCK for Video Processing Engine.

Signed-off-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2023-08-31 16:33:21 -04:00
Huang Rui
e784199c40 drm/amdgpu: add VPE IP BLOCK definition 
Add IP BLOCK for Video Processing Engine.

Signed-off-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2023-08-31 16:33:17 -04:00
Huang Rui
2d6ea3b07c drm/amdgpu: add VPE RING TYPE definition 
Add RING TYPE for Video Processing Engine.

Signed-off-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2023-08-31 16:33:09 -04:00
Lang Yu
2edc59309f drm/amdgpu: add VPE 6.1.0 header files 
Add initial headers. (Ray)
Update to align with hardware changes. (Lang)
Updates (Alex)

Signed-off-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Lang Yu <Lang.Yu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2023-08-30 15:51:17 -04:00
Srinivasan Shanmugam
8254e05c82 drm/amdgpu: Fix printk_ratelimit() with DRM_ERROR_RATELIMITED in 'amdgpu_cs_ioctl' 
Replaced printk_ratelimit() with its DRM equivalent to avoid flooding of
dmesg logs & hence fixes the following:

WARNING: Prefer printk_ratelimited or pr_<level>_ratelimited to printk_ratelimit
+               if (printk_ratelimit())

Cc: Christian König <christian.koenig@amd.com>
Cc: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Srinivasan Shanmugam <srinivasan.shanmugam@amd.com>
Reviewed-by: Guchun Chen <guchun.chen@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2023-08-30 15:51:17 -04:00
Hamza Mahfooz
fe320639c1 Revert "Revert "drm/amd/display: Implement zpos property"" 
This reverts commit e2066eb4ef.

The problematic IGT test case (i.e. kms_atomic@plane-immutable-zpos) has
been fixed as of commit cb77add45011 ("tests/kms_atomic: remove zpos <
N-planes assert") to the IGT repo. So, reintroduce the reverted code.

Link: cb77add450
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Melissa Wen <mwen@igalia.com>
Signed-off-by: Hamza Mahfooz <hamza.mahfooz@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2023-08-30 15:51:17 -04:00
Srinivasan Shanmugam
bf227a4f05 drm/amdgpu: Use READ_ONCE() when reading the values in 'sdma_v4_4_2_ring_get_rptr' 
Use READ_ONCE() instead of declaring the pointer volatile. To prevent
the compiler from refetching or reordering the read, so that the read
value is always consistent.

Link: https://lwn.net/Articles/624126/
Cc: Felix Kuehling <Felix.Kuehling@amd.com>
Cc: Guchun Chen <guchun.chen@amd.com>
Cc: Christian König <christian.koenig@amd.com>
Cc: Alex Deucher <alexander.deucher@amd.com>
Cc: "Pan, Xinhui" <Xinhui.Pan@amd.com>
Cc: Le Ma <le.ma@amd.com>
Cc: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Srinivasan Shanmugam <srinivasan.shanmugam@amd.com>
Reviewed-by: Le Ma <le.ma@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2023-08-30 15:51:17 -04:00
Yifan Zhang
4d5dc6260c drm/amdgpu: remove unused parameter in amdgpu_vmid_grab_idle 
amdgpu_vm is not used in amdgpu_vmid_grab_idle.

Signed-off-by: Yifan Zhang <yifan1.zhang@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2023-08-30 15:51:17 -04:00
Asad Kamal
80c74918aa drm/amdkfd: Replace pr_err with dev_err 
Replace pr_err with dev_err to show the bus-id of
failing device with kfd queue errors

Signed-off-by: Asad Kamal <asad.kamal@amd.com>
Reviewed-by: Lijo Lazar <lijo.lazar@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2023-08-30 15:51:17 -04:00
Darren Powell
ee78ef046c amdgpu/pm: Optimize emit_clock_levels for arcturus - part 2 
Use variables to remove ternary expression in print statement and
 improve readability. This will help to optimize the code duplication
 in the switch statement
 Also Changed:
  replaced single_dpm_table->count as iterator in for loops with safer
    clocks_num_levels value
  replaced dpm_table.value usage with local var clocks_mhz

Signed-off-by: Darren Powell <darren.powell@amd.com>
Reviewed-by: Lijo Lazar <lijo.lazar@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2023-08-30 15:51:17 -04:00
Darren Powell
f72dcf8b29 amdgpu/pm: Optimize emit_clock_levels for arcturus - part 1 
Use variables to remove the multiple nested ternary expressions and
 improve readability. This will help to optimize the code duplication
 in the switch statement
 Also Changed:
  Modify function arcturus_get_clk_table to void function as it
    always returns 0
  Use const string "attempt_string" to cut down on repetition

Signed-off-by: Darren Powell <darren.powell@amd.com>
Reviewed-by: Lijo Lazar <lijo.lazar@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2023-08-30 15:51:17 -04:00
Jay Cornwall
38498908c5 drm/amdkfd: Add missing gfx11 MQD manager callbacks 
mqd_stride function was introduced in commit 2f77b9a242
("drm/amdkfd: Update MQD management on multi XCC setup")
but not assigned for gfx11. Fixes a NULL dereference in debugfs.

Signed-off-by: Jay Cornwall <jay.cornwall@amd.com>
Signed-off-by: Harish Kasiviswanathan <Harish.Kasiviswanathan@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2023-08-30 15:51:16 -04:00
Hawking Zhang
bf7aa8bea9 drm/amdgpu: Free ras cmd input buffer properly 
Do not access the pointer for ras input cmd buffer
if it is even not allocated.

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Stanley Yang <Stanley.Yang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2023-08-30 15:51:16 -04:00
Srinivasan Shanmugam
eae3699175 drm/amd/display: Adjust kdoc for 'optc35_set_odm_combine' 
Fixes the following W=1 kernel build warning:

drivers/gpu/drm/amd/amdgpu/../display/dc/dcn35/dcn35_optc.c:46: warning: This comment starts with '/**', but isn't a kernel-doc comment. Refer Documentation/doc-guide/kernel-doc.rst
* Enable CRTC

Cc: Qingqing Zhuo <Qingqing.Zhuo@amd.com>
Cc: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Cc: Harry Wentland <harry.wentland@amd.com>
Cc: Aurabindo Pillai <aurabindo.pillai@amd.com>
Cc: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Srinivasan Shanmugam <srinivasan.shanmugam@amd.com>
Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2023-08-30 15:51:16 -04:00
Ma Jun
8f9a9a09af drm/amd: Simplify the bo size check funciton 
Simplify the code logic of size check function amdgpu_bo_validate_size

Signed-off-by: Ma Jun <Jun.Ma2@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2023-08-30 15:51:16 -04:00
Rajneesh Bhardwaj
d30279a9e3 drm/amdgpu: Hide xcp partition sysfs under SRIOV 
XCP partitions should not be visible for the VF for GFXIP 9.4.3.

Reviewed-by: Lijo Lazar <lijo.lazar@amd.com>
Signed-off-by: Rajneesh Bhardwaj <rajneesh.bhardwaj@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2023-08-30 15:51:16 -04:00
Harish Kasiviswanathan
37fb879107 drm/amdkfd: ratelimited SQ interrupt messages 
No functional change. Use ratelimited version of pr_ to avoid
overflowing of dmesg buffer

Signed-off-by: Harish Kasiviswanathan <Harish.Kasiviswanathan@amd.com>
Reviewed-by: Philip Yang <philip.yang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2023-08-30 15:51:16 -04:00
Tao Zhou
ac3343c761 drm/amdgpu: use read-modify-write mode for gfx v9_4_3 SQ setting 
Instead of using direct update, avoid touching unrelated fields.

Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2023-08-30 15:51:16 -04:00
ZhenGuo Yin
9f05cfc78c drm/amdgpu: access RLC_SPM_MC_CNTL through MMIO in SRIOV runtime 
Register RLC_SPM_MC_CNTL is not blocked by L1 policy, VF can
directly access it through MMIO during SRIOV runtime.

v2: use SOC15 interface to access registers

Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: ZhenGuo Yin <zhenguo.yin@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2023-08-30 15:51:16 -04:00