Stephen Boyd
abbe1eff90
clk: socfpga: Fix code formatting
...
This function's parameters are oddly formatted. Looks like a newline was
missed or something. Fix it.
Cc: Dinh Nguyen <dinguyen@kernel.org >
Link: https://lore.kernel.org/r/20210331023119.3294893-1-sboyd@kernel.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org >
2021-03-30 19:31:26 -07:00
Dinh Nguyen
ba7e258425
clk: socfpga: Convert to s10/agilex/n5x to use clk_hw
...
As recommended by Stephen Boyd, convert the Agilex/Stratix10/n5x clock
driver to use the clk_hw registration method.
Suggested-by: Stephen Boyd <sboyd@kernel.org >
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org >
Link: https://lore.kernel.org/r/20210302214151.1333447-3-dinguyen@kernel.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org >
2021-03-30 19:26:26 -07:00
Dinh Nguyen
a0f9819cbe
clk: socfpga: agilex: add clock driver for eASIC N5X platform
...
Add support for Intel's eASIC N5X platform. The clock manager driver for
the N5X is very similar to the Agilex platform, we can re-use most of
the Agilex clock driver.
This patch makes the necessary changes for the driver to differentiate
between the Agilex and the N5X platforms.
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org >
Link: https://lore.kernel.org/r/20210212143059.478554-2-dinguyen@kernel.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org >
2021-02-12 13:04:58 -08:00
YueHaibing
b10f224935
clk: socfpga: agilex: Remove unused variable 'cntr_mux'
...
drivers/clk/socfpga/clk-agilex.c:24:37: warning: ‘cntr_mux’ defined but not used [-Wunused-const-variable=]
static const struct clk_parent_data cntr_mux[] = {
^~~~~~~~
There is no caller in tree, so can remove it.
Signed-off-by: YueHaibing <yuehaibing@huawei.com >
Link: https://lore.kernel.org/r/20200915020950.4688-1-yuehaibing@huawei.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org >
2020-09-22 12:46:12 -07:00
Dinh Nguyen
44a7f3e822
clk: socfpga: agilex: mpu_l2ram_clk should be mpu_ccu_clk
...
Preliminary documentation documented the mpu_l2ram_clk, but since then,
the mpu_l2ram_clk is no longer documented. It's now referred to as
mpu_ccu_clk.
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org >
Link: https://lore.kernel.org/r/20200616202417.14376-3-dinguyen@kernel.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org >
2020-06-19 19:27:33 -07:00
Dinh Nguyen
6f3bcf56f8
clk: socfpga: agilex: add nand_x_clk and nand_ecc_clk
...
And the nand_x_clk and nand_ecc_clk. Make the nand_x_clk be the main
clock that is feeding the NAND IP and correct it's parent to be the
l4_mp_clk.
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org >
Link: https://lore.kernel.org/r/20200616202417.14376-2-dinguyen@kernel.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org >
2020-06-19 19:27:33 -07:00
Dinh Nguyen
80c6b7a089
clk: socfpga: agilex: add clock driver for the Agilex platform
...
For the most part the Agilex clock structure is very similar to
Stratix10, so we re-use most of the Stratix10 clock driver.
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org >
Link: https://lkml.kernel.org/r/20200512181647.5071-5-dinguyen@kernel.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org >
2020-05-26 19:13:05 -07:00
