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53 Commits

Author SHA1 Message Date
Geert Uytterhoeven
61232cd6ef pinctrl: renesas: r8a7791: Add bias pinconf support 
Implement support for pull-up (most pins) and pull-down (ASEBRK#/ACK)
handling for R-Car M2-W and M2-N, and RZ/G1M and RZ/G1N SoCs, using the
common R-Car bias handling.

Note that on RZ/G1 SoCs, the "ASEBRK#/ACK" pin is called "ACK", but the
code doesn't handle that naming difference.  Hence users should use the
R-Car naming in DTS files.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Link: https://lore.kernel.org/r/20210303132619.3938128-7-geert+renesas@glider.be
 2021-03-24 10:38:29 +01:00
Geert Uytterhoeven
1d3928a3e6 pinctrl: renesas: Add support for R-Car SoCs with pull-down only pins 
Currently, the common R-Car bias handling supports pin controllers with
either:
  1. Separate pin Pull-Enable (PUEN) and pin Pull-Up/Down control (PUD)
     registers, for controlling both pin pull-up and pin pull-down,
  2. A single pin Pull-Up control register (PUPR), for controlling pin
     pull-up.

Add support for a variant of #2, where some bits in the single pin
Pull-Up control register (PUPR) control pin pull-down instead of pin
pull-up.  This is the case for the "ASEBRK#/ACK" pin on R-Car M2-W,
M2-N, and E2, and the "ACK" pin on RZ/G1M, RZ/G1N, RZ/G1E, and RZ/G1C.
To describe such a register, SoC-specific drivers need to provide two
instances of pinmux_bias_reg: a first one with the puen field filled in,
listing pins with pull-up functionality, and a second one with the pud
field filled in, listing pins with pull-down functionality.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Link: https://lore.kernel.org/r/20210303132619.3938128-6-geert+renesas@glider.be
 2021-03-24 10:38:29 +01:00
Geert Uytterhoeven
93d6c7d676 pinctrl: renesas: Add PORT_GP_CFG_7 macros 
Add PORT_GP_CFG_7() and PORT_GP_7() helper macros, to be used by the
r8a7791 subdriver.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Link: https://lore.kernel.org/r/20210303132619.3938128-5-geert+renesas@glider.be
 2021-03-24 10:38:29 +01:00
Geert Uytterhoeven
ec0794a122 pinctrl: renesas: Factor out common R-Mobile bias handling 
The pin control sub-drivers for SH/R-Mobile SoCs contain almost
identical bias handling.  The only SoC-specific part is the mapping from
pin numbers to PORTnCR registers.

Reduce code duplication by factoring out the bias handling to the common
pinctrl.c code.  Use a callback to handle the pin/register mapping.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Link: https://lore.kernel.org/r/20210303132619.3938128-4-geert+renesas@glider.be
 2021-03-24 10:38:29 +01:00
Geert Uytterhoeven
4b6e6c1989 pinctrl: renesas: Move R-Car bias helpers to sh_pfc.h 
The Renesas Pin Function Controller driver uses two header files:
  - sh_pfc.h, for use by both core code and SoC-specific drivers,
  - core.h, for internal use by the core code only.

Hence move the R-Car bias helper declarations from core.h to sh_pfc.h,
and drop the inclusion of core.h from SoC-specific drivers that no
longer need it.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Link: https://lore.kernel.org/r/20210303132619.3938128-3-geert+renesas@glider.be
 2021-03-24 10:38:29 +01:00
Geert Uytterhoeven
b82fd2df17 pinctrl: renesas: Make sh_pfc_pin_to_bias_reg() static 
Now all R-Car pin control drivers have been converted to the common
R-Car bias handling, sh_pfc_pin_to_bias_reg() is only called from a
single place.  Move it from core.c to pinctrl.c, make it static, and
rename it to rcar_pin_to_bias_reg(), as it is specific to R-Car SoCs.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Link: https://lore.kernel.org/r/20210303132619.3938128-2-geert+renesas@glider.be
 2021-03-24 10:38:29 +01:00
Niklas Söderlund
f7adcca27e pinctrl: renesas: r8a77965: Add vin4_g8 and vin5_high8 pins 
This patch adds vin4_g8 and vin5_high8 support to the R8A77965 SoC.

Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Reviewed-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
Link: https://lore.kernel.org/r/20210309114930.2433711-5-niklas.soderlund+renesas@ragnatech.se
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2021-03-10 10:50:26 +01:00
Niklas Söderlund
2a9e4f74cd pinctrl: renesas: r8a77990: Add vin4_g8 and vin5_high8 pins 
This patch adds vin4_g8 and vin5_high8 support to the R8A77990 SoC.

Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Reviewed-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
Link: https://lore.kernel.org/r/20210309114930.2433711-4-niklas.soderlund+renesas@ragnatech.se
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2021-03-10 10:50:26 +01:00
Niklas Söderlund
3d250efb8c pinctrl: renesas: r8a7796: Add vin4_g8 and vin5_high8 pins 
This patch adds vin4_g8 and vin5_high8 support to the R8A7796 SoC.

Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Reviewed-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
Link: https://lore.kernel.org/r/20210309114930.2433711-3-niklas.soderlund+renesas@ragnatech.se
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2021-03-10 10:50:26 +01:00
Niklas Söderlund
5f79bbb28b pinctrl: renesas: r8a77951: Add vin4_g8 and vin5_high8 pins 
This patch adds vin4_g8 and vin5_high8 support to the R8A77951 SoC.

Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Reviewed-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
Link: https://lore.kernel.org/r/20210309114930.2433711-2-niklas.soderlund+renesas@ragnatech.se
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2021-03-10 10:50:26 +01:00
Linus Walleij
dbbdb8da42 Merge tag 'renesas-pinctrl-for-v5.12-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel 
pinctrl: renesas: Updates for v5.12

  - Restrict debug runtime-checks to Renesas platforms,
  - Initial support for the R-Car V3U SoC.
 2021-01-18 16:11:42 +01:00
Ulrich Hecht
a5cda861ed pinctrl: renesas: r8a779a0: Add TPU pins, groups and functions 
Add pins, groups and functions for the 16-Bit Timer Pulse Unit outputs
on the R-Car R8A779A0 (V3U) SoC.

Signed-off-by: Ulrich Hecht <uli+renesas@fpond.eu>
Link: https://lore.kernel.org/r/20210112165929.31002-13-uli+renesas@fpond.eu
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2021-01-14 12:06:16 +01:00
Ulrich Hecht
b3761cd6e1 pinctrl: renesas: r8a779a0: Add TMU pins, groups and functions 
This patch adds TMU TCLK1-4 pins, groups and functions to the R8A779A0
(V3U) SoC.

Signed-off-by: Ulrich Hecht <uli+renesas@fpond.eu>
Link: https://lore.kernel.org/r/20210112165929.31002-12-uli+renesas@fpond.eu
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2021-01-14 12:06:15 +01:00
Ulrich Hecht
a6a5140333 pinctrl: renesas: r8a779a0: Add QSPI pins, groups, and functions 
Add the QSPI0-1 pins, groups and functions to the R8A779A0 (V3U) PFC
driver.

Signed-off-by: Ulrich Hecht <uli+renesas@fpond.eu>
Link: https://lore.kernel.org/r/20210112165929.31002-11-uli+renesas@fpond.eu
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2021-01-14 12:06:15 +01:00
Ulrich Hecht
30db678101 pinctrl: renesas: r8a779a0: Add PWM pins, groups and functions 
This patch adds PWM0-4 pins, groups and functions to the R8A779A0 (V3U)
SoC.

Signed-off-by: Ulrich Hecht <uli+renesas@fpond.eu>
Link: https://lore.kernel.org/r/20210112165929.31002-10-uli+renesas@fpond.eu
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2021-01-14 12:06:15 +01:00
Ulrich Hecht
88aac7aa75 pinctrl: renesas: r8a779a0: Add MSIOF pins, groups and functions 
This patch adds MSIOF0-5 pins, groups and functions to R8A779A0 (V3U)
SoC.

Signed-off-by: Ulrich Hecht <uli+renesas@fpond.eu>
Link: https://lore.kernel.org/r/20210112165929.31002-9-uli+renesas@fpond.eu
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2021-01-14 12:06:15 +01:00
Ulrich Hecht
2feb2d5cba pinctrl: renesas: r8a779a0: Add MMC pins, groups and functions 
This patch adds MMC pins, groups and functions to R8A779A0 (V3U) SoC.

Signed-off-by: Ulrich Hecht <uli+renesas@fpond.eu>
Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Link: https://lore.kernel.org/r/20210112165929.31002-8-uli+renesas@fpond.eu
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2021-01-14 12:06:15 +01:00
Ulrich Hecht
8be8e8ee02 pinctrl: renesas: r8a779a0: Add INTC-EX pins, groups and function 
Add pins, groups, and function for the Interrupt Controller for External
Devices (INTC-EX) on the R-Car R8A779A0 (V3U) SoC.

Signed-off-by: Ulrich Hecht <uli+renesas@fpond.eu>
Link: https://lore.kernel.org/r/20210112165929.31002-7-uli+renesas@fpond.eu
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2021-01-14 12:06:15 +01:00
Ulrich Hecht
7e67ff6efc pinctrl: renesas: r8a779a0: Add HSCIF pins, groups and functions 
This patch adds HSCIF0-3 pins, groups and functions to the R8A779A0
(V3U) SoC.

Signed-off-by: Ulrich Hecht <uli+renesas@fpond.eu>
Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Link: https://lore.kernel.org/r/20210112165929.31002-6-uli+renesas@fpond.eu
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2021-01-14 12:06:15 +01:00
Ulrich Hecht
6e03446d0e pinctrl: renesas: r8a779a0: Add DU pins, groups and function 
This patch adds DU pins, groups and function for the R8A779A0 (V3U) SoC.

Signed-off-by: Ulrich Hecht <uli+renesas@fpond.eu>
Link: https://lore.kernel.org/r/20210112165929.31002-5-uli+renesas@fpond.eu
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2021-01-14 12:06:15 +01:00
Ulrich Hecht
1a954c6823 pinctrl: renesas: r8a779a0: Add CANFD pins, groups and functions 
This patch adds CANFD 0-7 and CANFD clock pinmux support for the
R8A779A0 (V3U) SoC.

Signed-off-by: Ulrich Hecht <uli+renesas@fpond.eu>
Link: https://lore.kernel.org/r/20210112165929.31002-4-uli+renesas@fpond.eu
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2021-01-14 12:06:15 +01:00
Ulrich Hecht
cc35593ff4 pinctrl: renesas: r8a779a0: Add EtherAVB pins, groups and functions 
This patch adds groups and function for AVB PHY, LINK, MAGIC, RGMII and
PTP pins for the R8A779A0 (V3U) SoC.

Signed-off-by: Ulrich Hecht <uli+renesas@fpond.eu>
Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Link: https://lore.kernel.org/r/20210112165929.31002-3-uli+renesas@fpond.eu
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2021-01-14 12:06:15 +01:00
Ulrich Hecht
7b66f2ddc8 pinctrl: renesas: r8a779a0: Add I2C pins, groups and functions 
This patch adds I2C0-6 pins, groups and functions to the R8A779A0 (V3U)
SoC.

Signed-off-by: Ulrich Hecht <uli+renesas@fpond.eu>
Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Link: https://lore.kernel.org/r/20210112165929.31002-2-uli+renesas@fpond.eu
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2021-01-14 12:06:15 +01:00
Ulrich Hecht
5621739dc1 pinctrl: renesas: r8a779a0: Add SCIF pins, groups and functions 
This patch adds SCIF0, 1, 3 and 4 pins, groups and functions for the
R8A779A0 (V3U) SoC.

Signed-off-by: Ulrich Hecht <uli+renesas@fpond.eu>
Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Link: https://lore.kernel.org/r/20210112165912.30876-6-uli+renesas@fpond.eu
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2021-01-14 12:06:15 +01:00
Ulrich Hecht
741a7370fc pinctrl: renesas: Initial R8A779A0 (V3U) PFC support 
This patch adds initial pinctrl support for the R8A779A0 (V3U) SoC,
including bias, drive strength and voltage control.

Based on patch by LUU HOAI <hoai.luu.ub@renesas.com>.

Signed-off-by: Ulrich Hecht <uli+renesas@fpond.eu>
Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Link: https://lore.kernel.org/r/20210112165912.30876-5-uli+renesas@fpond.eu
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2021-01-14 12:06:15 +01:00
Ulrich Hecht
9f2af9e561 pinctrl: renesas: Add PORT_GP_CFG_{2,31} macros 
Signed-off-by: Ulrich Hecht <uli+renesas@fpond.eu>
Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Link: https://lore.kernel.org/r/20210112165912.30876-4-uli+renesas@fpond.eu
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2021-01-14 12:06:15 +01:00
Ulrich Hecht
537db25ca3 pinctrl: renesas: Add I/O voltage level flag 
This patch adds config macros describing the voltage levels available on
a pin. The current default (3.3V/1.8V) maps to zero to avoid having to
change existing PFC implementations.

Signed-off-by: Ulrich Hecht <uli+renesas@fpond.eu>
Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Link: https://lore.kernel.org/r/20210112165912.30876-3-uli+renesas@fpond.eu
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2021-01-14 12:06:15 +01:00
Ulrich Hecht
e127ef2ed0 pinctrl: renesas: Implement unlock register masks 
The V3U SoC has several unlock registers, one per register group. They
reside at offset zero in each 0x200 bytes-sized block.

To avoid adding yet another table to the PFC implementation, this
patch adds the option to specify an address mask instead of the fixed
address in sh_pfc_soc_info::unlock_reg.

Signed-off-by: Ulrich Hecht <uli+renesas@fpond.eu>
Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Link: https://lore.kernel.org/r/20210112165912.30876-2-uli+renesas@fpond.eu
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2021-01-14 12:06:12 +01:00
Geert Uytterhoeven
6dd169fc20 pinctrl: renesas: checker: Restrict checks to Renesas platforms 
When DEBUG is defined (e.g. if CONFIG_DEBUG_PINCTRL=y), the Renesas pin
control driver runs sanity checks against the pin control tables.  This
may cause lots of output on the console, and can be annoying in ARM
multi-platform kernels.  Fix this by only running the checks when
running on SuperH, or on a DT platform supported by the Renesas pin
controller driver.

Suggested-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Arnd Bergmann <arnd@arndb.de>
Link: https://lore.kernel.org/r/20210111165013.496897-1-geert+renesas@glider.be
 2021-01-12 10:45:43 +01:00
Zhaoyu Liu
43878eb7c8 pinctrl: remove empty lines in pinctrl subsystem 
Remove all empty lines at the end of functions in pinctrl subsystem,
and make the code neat.

Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Reviewed-by: Geert Uytterhoeven <geert@linux-m68k.org>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Signed-off-by: Zhaoyu Liu <zackaryliu@yeah.net>
Link: https://lore.kernel.org/r/X98NP6NFK1Afzrgd@manjaro
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
 2021-01-05 16:09:24 +01:00
Gustavo A. R. Silva
7ba4a9591a pinctrl: renesas: Fix fall-through warnings for Clang 
In preparation to enable -Wimplicit-fallthrough for Clang, fix a warning
by explicitly adding a break statement instead of letting the code fall
through to the next case.

Link: https://github.com/KSPP/linux/issues/115
Signed-off-by: Gustavo A. R. Silva <gustavoars@kernel.org>
Link: https://lore.kernel.org/r/da20103af0c22424c5d08a12f7107771bf4c01c5.1605896059.git.gustavoars@kernel.org
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2020-11-23 09:47:28 +01:00
Lad Prabhakar
ffcd7f812d pinctrl: renesas: r8a77965: Add QSPI[01] pins, groups and functions 
Add pins, groups and functions for QSPIO[01].

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20201119130926.25692-5-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2020-11-23 09:43:28 +01:00
Lad Prabhakar
4356497e9e pinctrl: renesas: r8a7796: Add QSPI[01] pins, groups and functions 
Add pins, groups and functions for QSPIO[01].

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20201119130926.25692-4-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2020-11-23 09:43:28 +01:00
Lad Prabhakar
590567bf6f pinctrl: renesas: r8a77951: Add QSPI[01] pins, groups and functions 
Add pins, groups and functions for QSPIO[01].

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20201119130926.25692-3-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2020-11-23 09:43:27 +01:00
Lad Prabhakar
89ad953e1e pinctrl: renesas: r8a77990: Add QSPI[01] pins, groups and functions 
Add pins, groups and functions for QSPIO[01].

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20201119130926.25692-2-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2020-11-23 09:43:27 +01:00
Rikard Falkeborn
d4aac7d439 pinctrl: renesas: Constify sh73a0_vccq_mc0_ops 
The only usage of sh73a0_vccq_mc0_ops is to assign its address to the
ops field in the regulator_desc struct, which is a const pointer. Make
it const to allow the compiler to put it in read-only memory.

Signed-off-by: Rikard Falkeborn <rikard.falkeborn@gmail.com>
Link: https://lore.kernel.org/r/20201109221012.177478-1-rikard.falkeborn@gmail.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2020-11-13 15:37:41 +01:00
Geert Uytterhoeven
7b1425f08f pinctrl: renesas: Protect GPIO leftovers by CONFIG_PINCTRL_SH_FUNC_GPIO 
On SuperH and ARM SH/R-Mobile SoCs, the pin control driver handles
GPIOs, too.  To reduce code size when compiling a kernel supporting only
modern SoCs, most, but not all, of the GPIO functionality is protected
by checks for CONFIG_PINCTRL_SH_FUNC_GPIO.

Factor out the remaining parts when not needed:
  1. sh_pfc_soc_info.{in,out}put describe GPIO pins that have input
     resp. output capabilities (SuperH and SH/R-Mobile).
  2. sh_pfc_soc_info.gpio_irq{,_size} describe the mapping from GPIO
     pins to interrupt numbers (SH/R-Mobile).
  3. sh_pfc_gpio_set_direction() configures GPIO direction, called from
     the GPIO driver through pinctrl_gpio_direction_{in,out}put()
     (SH/R-Mobile).  Unfortunately this function cannot just be moved to
     drivers/pinctrl/renesas/gpio.c, as it relies on knowledge of
     sh_pfc_pinctrl, which is internal to
     drivers/pinctrl/renesas/pinctrl.c.

While code size reduction is minimal, this does help in documenting
depencies.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20201028151637.1734130-9-geert+renesas@glider.be
 2020-11-13 15:37:41 +01:00
Geert Uytterhoeven
a3ee0a246d pinctrl: renesas: r8a7778: Use common R-Car bias handling 
Currently, the rcar_pinmux_[gs]et_bias() helpers handle only SoCs that
have separate LSI Pin Pull-Enable (PUEN) and Pull-Up/Down Control (PUD)
registers, like R-Car Gen3 and RZ/G2.  Update the function to handle
SoCs that have only LSI Pin Pull-Up Control Register (PUPR), like R-Car
Gen1/Gen2 and RZ/G1.

Reduce code duplication by converting the R-Car M1A pin control driver
to use the common handler.

Note that this changes behavior in case the (invalid!) option
"bias-pull-down" is used in an R-Car M1A DTS: before, it was ignored
silently; after this change, it is considered the same as
"bias-pull-up".

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20201028151637.1734130-8-geert+renesas@glider.be
 2020-11-13 15:37:41 +01:00
Geert Uytterhoeven
2d341cc3da pinctrl: renesas: r8a7778: Use physical addresses for PUPR regs 
The handling of the LSI Pin Pull-Up Control Registers (PUPR) on R-Car
M1A uses register offsets instead of register physical addresses.
This is different from the handling on other R-Car parts.

Convert the bias handling from register offsets to physical addresses.
This increases uniformity, and prepares for consolidation of the bias
handling.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20201028151637.1734130-7-geert+renesas@glider.be
 2020-11-13 15:37:41 +01:00
Geert Uytterhoeven
27e768a4e7 pinctrl: renesas: Factor out common R-Car Gen3 bias handling 
All pin control drivers for R-Car Gen3 SoCs contain identical bias
handling.  Reduce code duplication by moving it to the common pinctrl.c
code.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20201028151637.1734130-6-geert+renesas@glider.be
 2020-11-13 15:37:41 +01:00
Geert Uytterhoeven
8019938a85 pinctrl: renesas: Optimize sh_pfc_pin_config 
Shrink sh_pfc_pin_config from 8 to 2 bytes:
  - The mux_set flag can be removed, as a non-zero mark value means the
    same (zero = PINMUX_RESERVED is an invalid mark value),
  - The gpio_enabled flag needs only a single bit,
  - Mark values are small integers, and can easily fit in a 15-bit
    bitfield.

This saves 6 bytes per pin when allocating the sh_pfc_pinctrl.configs
array, i.e. it reduces run-time memory consumption by ca. 1.5 KiB.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20201028151637.1734130-5-geert+renesas@glider.be
 2020-11-13 15:37:41 +01:00
Geert Uytterhoeven
eb9d673f94 pinctrl: renesas: Reorder struct sh_pfc_pin to remove hole 
On arm64, pointer size and alignment is 64-bit, hence a 4-byte hole is
present in between the enum_id and name members of the sh_pfc_pin
structure.  Get rid of this hole by sorting the structure's members by
decreasing size.

This saves up to 1.5 KiB per enabled SoC, and reduces the size of a
kernel including support for all R-Car Gen3 SoCs by more than 10 KiB.

This has no size impact on SH and arm32.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20201028151637.1734130-4-geert+renesas@glider.be
 2020-11-13 15:37:41 +01:00
Geert Uytterhoeven
b589f241d8 pinctrl: renesas: Singular/plural grammar fixes 
Fix a few singular vs. plural grammar issues in comments.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20201028151637.1734130-3-geert+renesas@glider.be
 2020-11-13 15:37:41 +01:00
Geert Uytterhoeven
b5bd0becfd pinctrl: renesas: Remove superfluous goto in sh_pfc_gpio_set_direction() 
Commit b13431ed6e ("pinctrl: sh-pfc: Remove incomplete flag
"cfg->type"") removed the last statement in between the goto and the
label.  Hence remove both.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20201028151637.1734130-2-geert+renesas@glider.be
 2020-11-13 15:37:41 +01:00
Biju Das
8d3b2e3d5b pinctrl: renesas: r8a7791: Optimize pinctrl image size for R8A774[34] 
This driver supports both RZ/G1[MN] and R-Car M2-W/M2-N SoCs.
Optimize pinctrl image size for RZ/G1[MN], when support for R-Car
M2-W/M2-N (R8A779[13]) is not enabled.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20201019124258.4574-7-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2020-11-13 15:37:41 +01:00
Biju Das
529b8eecb5 pinctrl: renesas: r8a7790: Optimize pinctrl image size for R8A7742 
This driver supports both RZ/G1H and R-Car H2 SoCs.
Optimize pinctrl image size for RZ/G1H, when support for R-Car H2
(R8A7790) is not enabled.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20201019124258.4574-6-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2020-11-13 15:37:41 +01:00
Biju Das
03522a59a9 pinctrl: renesas: r8a77990: Optimize pinctrl image size for R8A774C0 
This driver supports both RZ/G2E and R-Car E3 SoCs.
Optimize pinctrl image size for RZ/G2E, when support for R-Car E3
(R8A77990) is not enabled.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20201019124258.4574-5-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2020-11-13 15:37:41 +01:00
Biju Das
74c5fdc5b8 pinctrl: renesas: r8a77965: Optimize pinctrl image size for R8A774B1 
This driver supports both RZ/G2N and R-Car M3-N SoCs.
Optimize pinctrl image size for RZ/G2N, when support for R-Car M3-N
(R8A77965) is not enabled.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20201019124258.4574-4-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2020-11-13 15:37:41 +01:00
Biju Das
74ce7a8044 pinctrl: renesas: r8a7796: Optimize pinctrl image size for R8A774A1 
This driver supports both RZ/G2M and R-Car M3-W/W+ SoCs.
Optimize pinctrl image size for RZ/G2M, when support for R-Car M3-W/W+
(R8A7796[01]) is not enabled.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20201019132805.5996-1-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2020-11-13 15:37:38 +01:00
Biju Das
b8029394ef pinctrl: renesas: r8a77951: Optimize pinctrl image size for R8A774E1 
This driver supports both RZ/G2H and R-Car H3 ES2 SoCs.
Optimize pinctrl image size for RZ/G2H, when support for R-Car H3 ES2
(R8A77951) is not enabled.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20201019124258.4574-2-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2020-11-13 15:37:34 +01:00