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79 Commits

Author SHA1 Message Date
Chunming Zhou
d35db5617a drm/amdgpu: add hdp invalidation for gfx8 
Signed-off-by: Chunming Zhou <David1.Zhou@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2016-03-08 11:01:42 -05:00
Flora Cui
6157bd7a10 drm/amdgpu: fix rb bitmap & cu bitmap calculation 
Fix some copy paste typos.

Signed-off-by: Flora Cui <Flora.Cui@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2016-03-03 01:00:20 -05:00
Christian König
4ff37a83f1 drm/amdgpu: fix VM faults caused by vm_grab_id() v4 
The owner must be per ring as long as we don't
support sharing VMIDs per process. Also move the
assigned VMID and page directory address into the
IB structure.

v3: assign the VMID to all IBs, not just the first one.
v4: use correct pointer for owner

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2016-02-29 11:33:46 -05:00
Alex Deucher
aac1e3caac drm/amdgpu/gfx: fix off by one in rb rework (v2) 
When I reworked this code, I messed up num rb count.

v2: use hweight32

Reviewed-by: Ken Wang <Qingquing.Wang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2016-02-25 17:44:57 -05:00
Alex Deucher
549300ceae drm/amdgpu/vi: move uvd tiling config setup into uvd code 
Split uvd and gfx programming.

Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2016-02-12 15:53:14 -05:00
Alex Deucher
c458fe9425 drm/amdgpu/vi: move sdma tiling config setup into sdma code 
Split sdma and gfx programming.

Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2016-02-12 15:53:04 -05:00
Alex Deucher
8f8e00c17e drm/amdgpu/gfx: clean up harvest configuration (v2) 
Read back harvest configuration from registers and simplify
calculations.  No need to program the raster config registers.
These are programmed as golden registers and the user mode
drivers program them as well.

v2: rebase on Tom's patches

Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2016-02-12 15:47:18 -05:00
Christian König
e86f9ceee1 drm/amdgpu: move sync into job object 
No need to keep that for every IB.

Signed-off-by: Christian König <christian.koenig@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2016-02-10 14:17:24 -05:00
Christian König
a0332b56f6 drm/amdgpu: send SDMA/GFX IB tests directly to the ring again 
There is no point in sending them through the scheduler.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucer@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2016-02-10 14:17:22 -05:00
Christian König
b07c60c065 drm/amdgpu: move ring from IBs into job 
We can't submit to multiple rings at the same time anyway.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucer@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2016-02-10 14:17:20 -05:00
Christian König
9e5d53094c drm/amdgpu: make pad_ib a ring function v3 
The padding depends on the firmware version and we need that for BO moves as
well, not only for VM updates.

v2: new approach of making pad_ib a ring function
v3: fix typo in macro name

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucer@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2016-02-10 14:17:20 -05:00
Alex Deucher
6e9821b26d drm/amdgpu/gfx: minor code cleanup 
Drop needless function wrapper.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2016-02-10 14:17:15 -05:00
Christian König
a27de35caa drm/amdgpu: remove the ring lock v2 
It's not needed any more because all access goes through the scheduler now.

v2: Update commit message.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2016-02-10 14:16:58 -05:00
Christian König
5907a0d8af drm/amdgpu: cleanup sync_seq handling 
Not used any more without semaphores

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2016-02-10 14:16:52 -05:00
Alex Deucher
ea5e4c8731 drm/amdgpu: remove some more semaphore leftovers 
No longer needed since semaphores were removed.

Reviewed-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Chunming Zhou <David1.Zhou@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2016-02-10 14:16:51 -05:00
Chunming Zhou
2f4b940033 drm/amdgpu: clean up hw semaphore support in driver 
No longer used.

Signed-off-by: Chunming Zhou <David1.Zhou@amd.com>
Reviewed-by: Ken Wang  <Qingqing.Wang@amd.com>
Reviewed-by: Monk Liu <monk.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2016-02-10 14:16:49 -05:00
Alex Deucher
951e09624a drm/amdgpu: load MEC ucode manually on iceland 
The smc doesn't handle it.

Reviewed-by: Ken Wang <Qingqing.Wang@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
 2016-02-02 22:54:32 -05:00
Alex Deucher
97dde76a30 drm/amdgpu: don't load MEC2 on topaz 
Not validated.

Reviewed-by: Ken Wang <Qingqing.Wang@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
 2016-02-02 22:54:25 -05:00
Alex Deucher
1d22a454ec drm/amdgpu/gfx8: enable cp inst/reg error interrupts 
Enable CP register/instruction error interrupts. Useful
for debugging command stream problems.

Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2016-02-02 16:25:40 -05:00
Alex Deucher
7776a69386 drm/amdgpu: Add some tweaks to gfx 8 soft reset 
Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Ken Wang <Qingqing.Wang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2016-01-15 12:43:22 -05:00
Eric Huang
6e378858df drm/amd/amdgpu: add gfx clock gating support for Fiji. 
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com>
Signed-off-by: Eric Huang <JinHuiEric.Huang@amd.com>
 2015-12-21 16:42:35 -05:00
Jammy Zhou
e61710c59d drm/amdgpu: support per device powerplay enablement (v2) 
The amdgu_powerplay variable is global for multiple GPU instances.

v2: fold in Flora's module option change, protect adev reference in
macros

Signed-off-by: Jammy Zhou <Jammy.Zhou@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
 2015-12-21 16:42:27 -05:00
Rex Zhu
ba5c2a87b0 drm/amdgpu: disable legacy path of firmware check if powerplay is enabled 
Powerplay will use a different interface once it's integrated.  These
legacy pathes will be removed once powerplay is enabled by default.

Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Jammy Zhou <Jammy.Zhou@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
 2015-12-21 16:42:08 -05:00
Flora Cui
c27816a883 drm/amdgpu/gfx8: update PA_SC_RASTER_CONFIG:PKR_MAP only 
Use default value as a base.

Signed-off-by: Flora Cui <Flora.Cui@amd.com>
Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com>
 2015-12-11 11:13:41 -05:00
Flora Cui
3b55ddadef drm/amdgpu/gfx8: Enable interrupt on ME1_PIPE3 
Otherwise FW cannot see the RLC ACK for the memory clean request
It's for Stoney.

Signed-off-by: Flora Cui <Flora.Cui@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com>
 2015-12-11 11:13:40 -05:00
Tom St Denis
eb64526f5a amdgpu/gfxv8: Remove magic numbers from function gfx_v8_0_tiling_mode_table_init() 
Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
 2015-12-04 11:26:52 -05:00
Tom St Denis
0d07db7e10 amdgpu/gfxv8: Simplification in gfx_v8_0_enable_gui_idle_interrupt() 
Simplified the function by folding the two paths into one.

Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
 2015-12-04 11:26:50 -05:00
Tom St Denis
544b8a74c7 amdgpu/gfxv8: Simplification of gfx_v8_0_create_bitmask() 
Simplification of the function gfx_v8_0_create_bitmask().

Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
 2015-12-04 11:26:50 -05:00
Tom St Denis
90bea0abf6 amdgpu/gfxv8: Cleanup of gfx_v8_0_tiling_mode_table_init() (v2) 
Simplification and LOC reduction of function gfx_v8_0_tiling_mode_table_init()

v2: remove spurious break
bug: https://bugs.freedesktop.org/show_bug.cgi?id=93236

Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
 2015-12-04 11:26:49 -05:00
Tom St Denis
8cdacf4457 amdgpu/gfxv8: Add missing break to switch statement from states init code 
Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
 2015-12-02 15:54:33 -05:00
Alex Deucher
ccba7691a5 drm/amdgpu: add EDC support for CZ (v3) 
This adds EDC support for CZ.
EDC = Error Correction and Detection
This code properly initializes the EDC hardware and
resets the error counts.  This is done in late_init
since it requires the IB pool which is not initialized
during hw_init.

v2: fix the IB size as noted by Felix, fix shader pgm
register programming
v3: use the IB for the shaders as suggested by Christian

Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2015-12-02 15:54:26 -05:00
Flora Cui
5f2e816b29 drm/amdgpu: update Fiji's tiling mode table 
Change-Id: I925c15015390113f7e27746ec5751eaa6a92c2a7
Signed-off-by: Flora Cui <Flora.Cui@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
 2015-11-16 11:05:56 -05:00
Flora Cui
451f698bca drm/amdgpu: update fiji_mgcg_cgcg_init table 
Change-Id: If44b8057741c78208f1976f60f31b535c944d0bd
Signed-off-by: Flora Cui <Flora.Cui@amd.com>
Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com>
 2015-11-16 11:05:49 -05:00
Flora Cui
fa6760482b drm/amdgpu: update Fiji's mmPA_SC_RASTER_CONFIG value 
Change-Id: I6d138306a878450e5bf8a77a2f1aacc380a39fe5
Signed-off-by: Flora Cui <Flora.Cui@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
 2015-11-16 11:05:46 -05:00
Flora Cui
a7ca8ef930 drm/amdgpu: update Fiji's Golden setting 
Change-Id: Ic3f3bfce4767cc05d04f6eb24e22a0f3e7ceacaa
Signed-off-by: Flora Cui <Flora.Cui@amd.com>
Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com>
 2015-11-03 11:48:18 -05:00
Alex Deucher
b8b339ea3b drm/amdgpu: add some additional CZ revisions 
Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
 2015-10-28 11:53:49 -04:00
Samuel Li
e3c7656c22 drm/amdgpu: add GFX support for Stoney (v2) 
Stoney is GFX 8.1.

v2: update to latest golden settings

Signed-off-by: Samuel Li <samuel.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2015-10-21 12:20:32 -04:00
Christian König
b7e4dad3e1 drm/amdgpu: remove old lockup detection infrastructure 
It didn't worked to well anyway.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com>
 2015-10-21 11:35:12 -04:00
Alex Deucher
a3d5aaa836 drm/amdgpu/gfx8: set TC_WB_ACTION_EN in RELEASE_MEM packet 
This is the recommended setting from the hw team for newer
versions of the firmware.

Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
 2015-10-19 09:56:11 -04:00
Alex Deucher
0bde3a95ea drm/amdgpu: split gfx8 gpu init into sw and hw parts 
Calculate the driver state in sw_init and program the
registers in hw init.

Acked-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2015-10-07 23:48:21 -04:00
monk.liu
5c3422b0b1 drm/amdgpu: sync ce and me with SWITCH_BUFFER(2) 
we used to adopt wait_reg_mem to let CE wait before DE finish page
updating, but from Tonga+, CE doesn't support wait_reg_mem package so
this logic no longer works.

so here is another approach to do same thing:
Insert two of SWITCH_BUFFER at both front and end of vm_flush can
guarantee that CE not go further to process IB_const before vm_flush
done.

Insert two of SWITCH_BUFFER also works on CI, so remove legency method
to sync CE and ME

v2:
Insert double SWITCH_BUFFER at front of vm flush as well.

Signed-off-by: monk.liu <monk.liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
 2015-09-23 17:23:45 -04:00
Christian König
72d7668b5b drm/amdgpu: export reservation_object from dmabuf to ttm (v2) 
Adds an extra argument to amdgpu_bo_create, which is only used in amdgpu_prime.c.

Port of radeon commit 831b6966a6.

v2: fix up kfd.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
 2015-09-23 17:23:34 -04:00
Christian König
20a85ff846 drm/amdgpu: use write confirm for vm_flush() 
Make sure the CP waits for the write to be confirmed before
invalidating.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
 2015-09-23 17:23:30 -04:00
Anatoli Antonovitch
22c01cc483 drm/amdgpu: execution barrier after fence v2 
Insert wait for reg mem after EOP to fix potential issue with vm context switch

v2: move wait to vm_flush() use equal instead of greater than.

Signed-off-by: Anatoli Antonovitch <anatoli.antonovitch@amd.com>
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
 2015-09-23 17:23:30 -04:00
Alex Deucher
35c7a9526a drm/amdgpu: rename gmc_v8_0_init_compute_vmid 
It should be gfx_v8_0_init_compute_vmid since it's
part of the gfx block.

Acked-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2015-09-04 16:36:28 -04:00
Jammy Zhou
bddf802638 drm/amdgpu: set MEC doorbell range for Fiji 
Signed-off-by: Jammy Zhou <Jammy.Zhou@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
 2015-09-02 12:35:52 -04:00
Jammy Zhou
edff0e2826 drm/amdgpu: add insert_nop ring func and default implementation 
The insert_nop function is added to amdgpu_ring_funcs structure as
well as the default implementation

Signed-off-by: Jammy Zhou <Jammy.Zhou@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
 2015-09-02 12:24:43 -04:00
Christian König
b203dd9594 drm/amdgpu: fix zeroing all IB fields manually v2 
The problem now is that we don't necessarily call amdgpu_ib_get()
in some error paths and so work with uninitialized data.

Better require that the memory is already zeroed.

v2: better commit message

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Chunming Zhou <david1.zhou@amd.com> (v1)
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
 2015-08-20 17:05:34 -04:00
Chunming Zhou
281b422301 drm/amdgpu: add reference for **fence 
fix fence is released when pass to **fence sometimes.
add reference for it.

Signed-off-by: Chunming Zhou <david1.zhou@amd.com>
Reviewed-by: Christian K?nig <christian.koenig@amd.com>
 2015-08-17 16:51:17 -04:00
Chunming Zhou
1763552ee8 drm/amdgpu: add kernel fence in ib_submit_kernel_helper 
every sbumission should be able to get a fence.

Signed-off-by: Chunming Zhou <david1.zhou@amd.com>
Reviewed-by: Christian K?nig <christian.koenig@amd.com>
Reviewed-by: Jammy Zhou <jammy.zhou@amd.com>
 2015-08-17 16:50:54 -04:00