raspi/linux
1
0
Fork 1
mirror of https://github.com/raspberrypi/linux.git synced 2025-12-21 09:12:05 +00:00
Code Issues Projects Releases Wiki Activity
916,765 Commits 105 Branches 108 Tags
b6e4bc125fc517969f97d901b1845ebf47bbea26
Commit Graph

7117 Commits

Author SHA1 Message Date
Xiaojie Yuan
b5c7385640 drm/amdgpu/discovery: move common discovery code out of navi1*_reg_base_init() 
move amdgpu_discovery_reg_base_init() from navi1*_reg_base_init() to a
common function nv_reg_base_init().

Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-08-06 13:53:05 -05:00
tiancyin
35ef88fa11 drm/amdgpu/soc15: fix external_rev_id for navi14 
fix the hard code external_rev_id.

Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: tiancyin <tianci.yin@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-08-06 13:52:58 -05:00
Tao Zhou
2a3c7ff6e3 drm/amdgpu: update ras sysfs feature info 
remove confused ras error type info

Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-08-06 13:52:52 -05:00
xinhui pan
876923fb92 drm/amdgpu: Fix panic during gpu reset 
Clear the flag after hw suspend, otherwise it skips the corresponding hw
resume.

Signed-off-by: xinhui pan <xinhui.pan@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-08-06 13:52:37 -05:00
Likun Gao
1f288afc2c drm/amdgpu: pin the csb buffer on hw init for gfx v8 
Without this pin, the csb buffer will be filled with inconsistent
data after S3 resume. And that will causes gfx hang on gfxoff
exit since this csb will be executed then.

Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Tested-by: Paul Gover <pmw.gover@yahoo.co.uk>
Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
Reviewed-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-08-06 13:52:31 -05:00
Gerd Hoffmann
5a5011a724 drm/amdgpu: switch driver from bo->resv to bo->base.resv 
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Link: http://patchwork.freedesktop.org/patch/msgid/20190805140119.7337-14-kraxel@redhat.com
 2019-08-06 08:21:54 +02:00
Gerd Hoffmann
b96f3e7c80 drm/ttm: use gem vma_node 
Drop vma_node from ttm_buffer_object, use the gem struct
(base.vma_node) instead.

Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Link: http://patchwork.freedesktop.org/patch/msgid/20190805140119.7337-9-kraxel@redhat.com
 2019-08-06 08:21:54 +02:00
Gerd Hoffmann
c105de2828 drm/amdgpu: use embedded gem object 
Drop drm_gem_object from amdgpu_bo, use the
ttm_buffer_object.base instead.

Build tested only.

Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Link: http://patchwork.freedesktop.org/patch/msgid/20190805140119.7337-6-kraxel@redhat.com
 2019-08-06 08:21:54 +02:00
Christian König
0dbd555a01 dma-buf: add more reservation object locking wrappers 
Complete the abstraction of the ww_mutex inside the reservation object.

This allows us to add more handling and debugging to the reservation
object in the future.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/320761/
 2019-08-05 09:28:43 +02:00
Thong Thai
d1836f3813 drm/amd/amdgpu/vcn_v2_0: Move VCN 2.0 specific dec ring test to vcn_v2_0 
VCN 2.0 firmware now requires a packet start command to be sent before
any other decode ring buffer command.

Signed-off-by: Thong Thai <thong.thai@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-08-02 10:36:35 -05:00
Thong Thai
af655cc5aa drm/amd/amdgpu/vcn_v2_0: Mark RB commands as KMD commands 
Sets the CMD_SOURCE bit for VCN 2.0 Decoder Ring Buffer commands. This
bit was previously set by the RBC HW on older firmware. Newer firmware
uses a SW RBC and this bit has to be set by the driver.

Signed-off-by: Thong Thai <thong.thai@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-08-02 10:36:34 -05:00
shaoyunl
3cf7bf2e48 drm/amdgpu: enable Navi12 kfd support for amdgpu 
Navi12 has the same interface as Navi10

Signed-off-by: shaoyunl <shaoyun.liu@amd.com>
Reviewed-by: Jack Xiao <Jack.Xiao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-08-02 10:30:41 -05:00
Leo Li
078655d982 drm/amdgpu: Add nv12 DC ip block 
Load DC and amdgpu display manager

Signed-off-by: Leo Li <sunpeng.li@amd.com>
Reviewed-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-08-02 10:30:41 -05:00
Boyuan Zhang
400e9c5ea6 drm/amdgpu: enable DPG mode for Navi12 
Enable Dynamic Power Gating VCN for Navi12.

Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-08-02 10:30:41 -05:00
Boyuan Zhang
1fbed280a2 drm/amdgpu: add VCN ip block for Navi12 
Add VCN2 ip block for Navi12

Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-08-02 10:30:41 -05:00
Boyuan Zhang
a3219816c4 drm/amdgpu: add Navi12 VCN firmware support 
Add Navi12 to VCN family

Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-08-02 10:30:41 -05:00
Xiaojie Yuan
6b66ae2e55 drm/amdgpu: add psp ip block for navi12 
Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Jack Xiao <Jack.Xiao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-08-02 10:30:41 -05:00
Xiaojie Yuan
7f47efeb9e drm/amdgpu: add smu ip block for navi12 
Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Jack Xiao <Jack.Xiao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-08-02 10:30:41 -05:00
Xiaojie Yuan
e60cc94b26 drm/amdgpu: start autoload till RLCG fw for navi12 
rlc save restore list is not ready yet for navi12

Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Jack Xiao <Jack.Xiao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-08-02 10:30:41 -05:00
Xiaojie Yuan
739cdbd6a2 drm/amdgpu/psp11: add psp support for navi12 
Same as other navi asics.

Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-08-02 10:30:41 -05:00
Jack Xiao
02938eed74 drm/amdgpu: correct smu rlc handshake enablement bit 
Correct the enablement bit of SMU RLC handshake.

Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-08-02 10:30:41 -05:00
Xiaojie Yuan
c726fbf0fb drm/amdgpu/sdma5: add golden settings for navi12 (v2) 
common golden settings are put in golden_settings_sdma_5 array

v2: update settings (Alex)

Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Jack Xiao <Jack.Xiao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-08-02 10:30:40 -05:00
Xiaojie Yuan
f8984cb9e3 drm/amdgpu/gfx10: add golden settings for navi12 (v2) 
Add initial golden settings for navi12 gfx.

v2: update settings

Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Jack Xiao <Jack.Xiao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-08-02 10:30:40 -05:00
Xiaojie Yuan
7990202903 drm/amdgpu: enable virtual display for navi12 
Virtual display is a sw display interface for
bring up and virtualization or for cards without
display hardware.

Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-08-02 10:30:40 -05:00
Xiaojie Yuan
71745cf474 drm/amdgpu/gfx10: set tcp harvest for navi12 
Same as navi10.

Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-08-02 10:30:40 -05:00
Xiaojie Yuan
44e9e7c96c drm/amdgpu: add ip blocks for navi12 
Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-08-02 10:30:40 -05:00
Xiaojie Yuan
4a0e815fb3 drm/amdgpu/gmc10: set gart size and vm size for navi12 
Same as other navi asics.

Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-08-02 10:30:40 -05:00
Xiaojie Yuan
f2d6731d77 drm/amdgpu/sdma5: add placeholder for navi12 golden settings 
None yet.

Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-08-02 10:30:40 -05:00
Xiaojie Yuan
6f523fd7b3 drm/amdgpu/sdma5: declare sdma firmwares for navi12 
Declare the firmwares and load the proper ones for navi12.

Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-08-02 10:30:40 -05:00
Xiaojie Yuan
4cdfc4a2be drm/amdgpu/gfx10: set rlc funcs for navi12 
Same as other navi asics.

Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-08-02 10:30:40 -05:00
Xiaojie Yuan
9ff3dba6d6 drm/amdgpu/gfx10: set number of me(c)/pipe/queue for navi12 
Same as other navi asics.

Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-08-02 10:30:40 -05:00
Xiaojie Yuan
716e9bb099 drm/amdgpu/gfx10: add placeholder for navi12 golden settings 
Not used yet.

Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-08-02 10:30:40 -05:00
Xiaojie Yuan
92c123aec1 drm/amdgpu/gfx10: declare cp/rlc firmwares for navi12 
Set the name properly to load the right ucode.

Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-08-02 10:30:40 -05:00
Xiaojie Yuan
6983469c1a drm/amdgpu/gfx10: add gfx config for navi12 
got from mmCP_MAX_CONTEXT and mmPA_SC_FIFO_SIZE

v2: squash all navi asics together because the
settings are the same.

Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-08-02 10:30:40 -05:00
Xiaojie Yuan
59ab8c292b drm/amdgpu/gfx10: set gfx cg for navi12 
Same as other navi asics.

Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-08-02 10:30:40 -05:00
Xiaojie Yuan
7e17e58bdd drm/amdgpu: set nbio/hdp cg for navi12 
Same as navi10.

Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-08-02 10:30:40 -05:00
Xiaojie Yuan
74b5e509a0 drm/amdgpu: initialize cg/pg flags and external rev id for navi12 
don't enable any cg/pg features yet.

v2: calculate external revision id from revision id so that we can
    differentiate navi12 A0 from A1 directly.

Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-08-02 10:30:40 -05:00
Xiaojie Yuan
d4d838ba4e drm/amdgpu: use front door firmware loading for navi12 
Same as other navi asics.

Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-08-02 10:30:40 -05:00
Xiaojie Yuan
4808cf9c2a drm/amdgpu: set asic family and ip blocks for navi12 
same with navi10

Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-08-02 10:30:39 -05:00
Xiaojie Yuan
42b325e5ec drm/amdgpu: add gpu_info firmware for navi12 
gpu_info firmare store asic configuration details.

Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-08-02 10:30:39 -05:00
Xiaojie Yuan
9802f5d78b drm/amdgpu: add navi12 asic type 
Add asic type.

Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-08-02 10:30:39 -05:00
Xiaojie Yuan
03d0a073cf drm/amdgpu: initialize reg base for navi12 
Set up the register offset map for navi12.

Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-08-02 10:30:39 -05:00
John Clements
8c2ef8ca0e drm/amdgpu: update SDMA V4 microcode init 
Removed loading duplicate instances of SDMA FW for Arcturus.
We use a single image for all instances.

Signed-off-by: John Clements <john.clements@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-08-02 10:30:39 -05:00
John Clements
b86f8d8b2b drm/amdgpu: extend PSP FW loading support to 8 SDMA instances 
Arcturus has 8 instances of SDMA.  Update host to PSP interface
to handle it.

Signed-off-by: John Clements <john.clements@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-08-02 10:30:39 -05:00
John Clements
8fda90e821 drm/amdgpu: disable MEC2 JT context init for Arcturus 
We don't need to handle it like other asics.

Signed-off-by: John Clements <john.clements@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-08-02 10:30:39 -05:00
John Clements
6c37bde9c6 drm/amdgpu: update PSP CMD fail response status print 
Print the response in hex with the apprpriate mask.

Signed-off-by: John Clements <john.clements@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-08-02 10:30:39 -05:00
John Clements
dc0d962297 drm/amdgpu: add PSP KDB loading support for Arcturus 
Add support for the arcturus specific psp metadata to the
amdgpu firmware and properly parse it when loading it.

Signed-off-by: John Clements <john.clements@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-08-02 10:30:39 -05:00
John Clements
f36d9ab95f drm/amdgpu: add PSP SW init support for Arcturus 
Add arcturus cases to psp init sewquence.

Signed-off-by: John Clements <john.clements@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-08-02 10:30:39 -05:00
John Clements
c0dac3c9f5 drm/amdgpu: removed duplicate line 
Remove duplicate break.

Signed-off-by: John Clements <john.clements@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-08-02 10:30:39 -05:00
Evan Quan
4abc1765d2 drm/amd/powerplay: enable SW SMU power profile switch support in KFD 
Hook up the SW SMU power profile switch in KFD routine.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-08-02 10:30:39 -05:00