Commit Graph

3496 Commits

Author SHA1 Message Date
Duje Mihanović
3b99cd274e clk: pxa910: Move number of clocks to driver source
The number of clocks should not be in the dt binding as it is not used
by the respective device tree and thus needlessly bloats the ABI.

Move this number of clocks into the driver source.

Signed-off-by: Duje Mihanović <duje.mihanovic@skole.hr>
Link: https://lore.kernel.org/r/20230812-mmp-nr-clks-v2-4-f9271bd7eaa5@skole.hr
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-08-22 14:14:17 -07:00
Duje Mihanović
87f06247e0 clk: pxa1928: Move number of clocks to driver source
The number of clocks should not be in the dt binding as it is not used
by the respective device tree and thus needlessly bloats the ABI.

Move this number of clocks into the driver source.

Signed-off-by: Duje Mihanović <duje.mihanovic@skole.hr>
Link: https://lore.kernel.org/r/20230812-mmp-nr-clks-v2-3-f9271bd7eaa5@skole.hr
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-08-22 14:14:14 -07:00
Duje Mihanović
51fa6aa5c2 clk: pxa168: Move number of clocks to driver source
The number of clocks should not be in the dt binding as it is not used
by the respective device tree and thus needlessly bloats the ABI.

Move this number of clocks into the driver source.

Signed-off-by: Duje Mihanović <duje.mihanovic@skole.hr>
Link: https://lore.kernel.org/r/20230812-mmp-nr-clks-v2-2-f9271bd7eaa5@skole.hr
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-08-22 14:14:06 -07:00
Duje Mihanović
46c13513a4 clk: mmp2: Move number of clocks to driver source
The number of clocks should not be in the dt binding as it is not used
by the respective device tree and thus needlessly bloats the ABI.

Move this number of clocks into the driver source.

Signed-off-by: Duje Mihanović <duje.mihanovic@skole.hr>
Link: https://lore.kernel.org/r/20230812-mmp-nr-clks-v2-1-f9271bd7eaa5@skole.hr
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-08-22 14:13:45 -07:00
Arnd Bergmann
c708140e96 Merge tag 'socfpga_dts_updates_for_v6.6' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux into soc/dt
SoCFPGA DTS updates for v6.6
- Fix dtbs_check warnings for usbphy, sram, rstmgr, memory, partitions
- Updated "stmmaceth-ocp" reset-names to "ahb" for stmmac ethernet
- Add initial support for Agilex5

* tag 'socfpga_dts_updates_for_v6.6' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux:
  arm64: dts: agilex5: add initial support for Intel Agilex5 SoCFPGA
  dt-bindings: clock: add Intel Agilex5 clock manager
  dt-bindings: reset: add reset IDs for Agilex5
  dt-bindings: intel: Add Intel Agilex5 compatible
  arm64: dts: socfpga: change the reset-name of "stmmaceth-ocp" to "ahb"
  arm64: dts: socfpga: n5x/stratix10: fix dtbs_check warning for partitions
  arm64: dts: agilex/stratix10: Updated QSPI Flash layout for UBIFS
  arm64: dts: agilex/stratix10/n5x: fix dtbs_check for rstmgr
  arm64: dts: stratix10/agilex/n5x: fix dtbs_check warning for memory node
  arm64: dts: socfpga: stratix10: fix dtbs_check warning for usbphy
  arm64: dts: socfpga: agilex/stratix10: fix dtbs_check warnings for sram

Link: https://lore.kernel.org/r/20230819161418.931258-1-dinguyen@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2023-08-21 21:49:00 -04:00
Arnd Bergmann
6522fbd48a Merge tag 'qcom-arm64-for-6.6' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into soc/dt
Qualcomm ARM64 DeviceTree updates for v6.6

Initial support for the SM4450 platform and the QRD device thereon is
added.

The IPQ5018 platform is introduced, and the RDP432-C2 board thereon.

A shared definition of the IPQ5332 RDP is introduced, as is GPIO-based
LEDs and buttons.

On the IPQ9574 RDP433 USB, CPU cooling maps and regulators are added.

On MSM8916, the D3 camera mezzanine is improved and refactored out to
its own dts. The Samsung Galaxy S4 Mini gains support for its PMIC with
charger, while Samsung Galaxy J5 and E5 gains touchscreen support.

A few fixes for MSM8939 are introduced, and initial support for Samsung
Galaxy A7 is add.

Support for scaling the cache bus fabric is introduced on MSM8996. A
missing interrupt for the USB2 controller is added. The touchscreen vio
supply on Xiaomi Mi 5 is corrected, and a few other cleanups are
introduces across other devices.

The display controller is introduced for MSM8998, a few clock fixes are
introduced and missing power domains are added for the multimedia
subsystem iommu.

Reserved memory-regions and reserved GPIO lists are updated for the
QDU/QRU1000 IDPs.

USB3 PHY is added to the QCM2290, the RB1 gains regulators and GPU is
enabled for the RB2.

PCIe and Ethernet support is introduced on SA8775P, and enabled for the
Ride board.

On SC7180 the PSCI integration is refactored, to allow supporting
devices with the Qualcomm firmware. BWMON is introduced, alongside the
CPUfreq-based bus voting.

A number of fixes are added for SC8180X, on the Primus and Lenovo Flex
5G devices pmic_glink is introduced and wired up, to provide support for
external display.

Missing SCM interconnect is added to SC8280XP, and the PDC is marked as
wakeup-parent of TLMM. On the CRD the gpio for vreg_misc_3p3 is
corrected and a few regulators are renamed to align with schematics. The
Lenovo Thinkpad X13s gains camera activity LED and a set of previously
reserved GPIOs are released. The SA8540P Ride platform gains RTC
support.

For SDM670 CPU and L3 frequency scaling is added, the PDC is introduced
and wired up as wakeup-parent of the TLMM.

On SDM845 the UFS controller gains interconnect path description,
power-domain information is added to GCC and minimum frequency of the
UFS ICE is corrected. On RB3 continuous splash memory region is
described, and the camera subsystem is enabled. On the Lenovo Yoga C630
a missing power supply for the display panel is added, and the debug
UART is introduced.

SDX75 RPMh power-domains and SPMI controller are introduces, the PMX75
PMIC is described and added to the IDP.

GPU description is added to SM6115, and together with display enabled on
the Lenovo Tab P11.

On SM635 BWMON is introduced for LLCC and DDR scaling. Display and GPU
is added, and the PDC is registered as wakeup-parent of TLMM.

L3 cache scaling is introduced on SM6375.

The DSI PHY compatible and an interrupt for I2C7 are corrected for
SM8150, on the Sony Xperia 1 and 5 the ramoops pmsg size is corrected.

On SM8250 BWMONs are introduced for DDR and LLCC scaling, the UFS node
gains interconnect paths, SMMU is marked as DMA coherent and dynamic
power coefficients are updated. On Sony Xperia 1 II and 5 II GPIO line
names are updated.

On SM8350 missing cluster sleep states and LMH interrupts are added,
the CPU compatibles are corrected and APR and LPASS pinctrl support is
introduced. The HDK gains uSD card support and PMK8350 is added.

For SM8450 support for RNG and RPMh stats are added, the ICE handling is
extracted from the UFS node and the display subsystem gains a missing
interconnect path. Thermal description is improved for the HDK.

On SM8550 MTP and QRD the pmic_glink is introduced, to provide
DisplayPort output. A missing regulator supply is also added.

A few platforms that happens to share the RPMH power-domain resource
identifier constants are migrated to new generic defines. ADC channel
names are generalized on various PMICs.

A variety of devices gain chassis-type, and the GIC_SPI constant is
replacing the 0 across a few different platforms.

* tag 'qcom-arm64-for-6.6' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: (215 commits)
  arm64: dts: qcom: sdm845-db845c: Mark cont splash memory region as reserved
  arm64: dts: qcom: sm6350: Hook up PDC as wakeup-parent of TLMM
  arm64: dts: qcom: sdm670: Hook up PDC as wakeup-parent of TLMM
  arm64: dts: qcom: sa8775p: Hook up PDC as wakeup-parent of TLMM
  arm64: dts: qcom: sc8280xp: Hook up PDC as wakeup-parent of TLMM
  arm64: dts: qcom: sdm670: Add PDC
  arm64: dts: qcom: msm8916-samsung-e5: Add touchscreen
  arm64: dts: qcom: sc7180: Split up TF-A related PSCI configuration
  arm64: dts: qcom: sc8280xp-x13s: Add camera activity LED
  arm64: dts: qcom: sc8280xp-x13s: Unreserve NC pins
  arm64: dts: qcom: msm8998: Add DPU1 nodes
  arm64: dts: qcom: msm8996: Fix dsi1 interrupts
  arm64: dts: qcom: sdx75-idp: Add regulator nodes
  arm64: dts: qcom: sdx75: Add rpmhpd node
  arm64: dts: qcom: sdx75-idp: Add pmics supported in SDX75
  arm64: dts: qcom: Add pmx75 PMIC dtsi
  arm64: dts: qcom: Add pm7550ba PMIC dtsi
  arm64: dts: qcom: Add pinctrl gpio support for pm7250b
  arm64: dts: qcom: sdx75: Add spmi node
  arm64: dts: qcom: msm8998: Add missing power domain to MMSS SMMU
  ...

Link: https://lore.kernel.org/r/20230819034551.2537866-1-andersson@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2023-08-21 21:38:09 -04:00
Arnd Bergmann
aa2951a8fa Merge tag 'stm32-dt-for-v6.6-1' of git://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32 into soc/dt
STM32 DT for v6.6, round 1

Highlights:
----------

- MCU:
  - Add CAN support on stm32f746.
  - Add touchscreen support (edt-ft5306) on stm32f746-disco.
  - Add support to Rocktech RK043FN48H display on stm32f746-disco
    board.
  - Add gpio-ranges for stm32f7 to fix boot issue.

- MPU:
  - STM32MP13:
    - Remove shmem for scmi-optee to match with OP-TEE configuration.
    - Enable OP-TEE asynchronous notification by using PPI#15.
    - Expose and use SCMI regulators on stm32mp135f-dk.

  - STMP32MP15:
    - Remove shmem for scmi-optee to match with OPTEE configuration
    - Deduplicate DSI node to fix  #address-cells/#size-cells issue on
      boards using it.

  - ST:
    - Fix dts check warnings on stm32mp15-scmi boards.

  - DH:
    - Add missing detach mailbox for DHCOM and DHCOR SoM.

  - Odyssey:
    - Add missing detach mailbox for Odyssey SoM.

  - OCTAVO:
    - Add Linux Automation Test Automation Controller (LXA TAC) based
      on Octavo Systems OSD32MP15x SiP. It contains: eMMC,
      DSA-capable ETH switch (2 ports), dual CAN...
      It adds two boards support: lxa-tac-gen1 and lxa-tac-gen2 based
      on STM32MP157.

  - PROTONIC:
    - Add Power over Data Line (PoDL) Power Source Equipment (PSE)
      regulator nodes on PRTT1C board. It allows power delivery and
      data transmission over a single twisted pair.

* tag 'stm32-dt-for-v6.6-1' of git://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32: (29 commits)
  ARM: dts: stm32: add SCMI PMIC regulators on stm32mp135f-dk board
  ARM: dts: stm32: STM32MP13x SoC exposes SCMI regulators
  dt-bindings: rcc: stm32: add STM32MP13 SCMI regulators IDs
  ARM: dts: stm32: support display on stm32f746-disco board
  ARM: dts: stm32: rename mmc_vcard to vcc-3v3 on stm32f746-disco
  ARM: dts: stm32: add pin map for LTDC on stm32f7
  ARM: dts: stm32: add ltdc support on stm32f746 MCU
  ARM: dts: st: Add gpio-ranges for stm32f769-pinctrl
  ARM: dts: st: Add gpio-ranges for stm32f746-pinctrl
  ARM: dts: st: stm32mp157c-emstamp: correct regulator-active-discharge
  ARM: dts: st: stm32mp157c-emstamp: drop incorrect vref_ddr property
  ARM: dts: stm32: fix dts check warnings on stm32mp15-scmi
  ARM: dts: stm32: Add missing detach mailbox for DHCOR SoM
  ARM: dts: stm32: Add missing detach mailbox for DHCOM SoM
  ARM: dts: stm32: Add missing detach mailbox for Odyssey SoM
  ARM: dts: stm32: Add missing detach mailbox for emtrion emSBC-Argon
  ARM: dts: stm32: prtt1c: Add PoDL PSE regulator nodes
  ARM: dts: stm32: add touchscreen on stm32f746-disco board
  ARM: dts: stm32: add pin map for i2c3 controller on stm32f7
  ARM: dts: stm32: re-add CAN support on stm32f746
  ...

Link: https://lore.kernel.org/r/c0524a16-ab27-0cb5-8e7b-c12f7bde7e0d@foss.st.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2023-08-21 21:25:23 -04:00
Arnd Bergmann
9eb33ddedd Merge tag 'qcom-drivers-for-6.6' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into soc/drivers
Qualcomm driver updates for v6.6

Compatible and clock handling in the Qualcomm SCM driver is cleaned up,
together with a couple stylistic cleanups and transition to mark
exported symbols GPL only.

An abstraction for the RPM subsystem is introduced, to make align the
structure of the SMD and GLINK nodes thereof with the structure when a
remoteproc is involved. This is done to facilitate associating
additional entities with the RPM subsystem.

The qmp_send() API is modified to not expose hardware requirements onto
the client drivers, and then further extended to allow command
formatting directly in the API, to facilitate this typical use case.

In the Qualcomm Command DB driver, NUL characters previously included in
identifiers are dropped from the debugfs, to facilitate scripting.

The thresholds of the BWMON driver are simplified to avoid hard coded
starting values.

The OCMEM driver is updated with some cleanups and fixes, and addition
of MSM8226 support.

PMIC_GLINK gains support for retimer switches, safe mode is selected
when the cable is disconnected from altmode and the same is enabled for
SM8550.

An off-by-one string length check is corrected in the QMI encoder
decoder library.

The RPMh tracepoints are extended to include the state of the request,
to provide needed context in the traced events.

The series from Ulf creating a genpd framework is integrated, to
facilitate the other changes to the cpr, rpmpd and rpmhpd driver.
SDX75 support is added to the rpmhpd driver, and the rpmpd driver is
extended with the same sync_state logic found in the rpmhpd driver.

The socinfo driver gains knowledge about SM4450 and SM7125, the IPQ5019
platform is dropped.

Clock handling in the GSBI driver is cleaned up with the use of
devm_clk_get_enabled().

The list of VMIDs defined for the SCM assign memory interface is
extended.

* tag 'qcom-drivers-for-6.6' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: (52 commits)
  soc: qcom: aoss: Tidy up qmp_send() callers
  soc: qcom: aoss: Format string in qmp_send()
  soc: qcom: aoss: Move length requirements from caller
  dt-bindings: firmware: qcom: scm: Updating VMID list
  dt-bindings: qcom: Update RPMHPD entries for some SoCs
  soc: qcom: qmi_encdec: Restrict string length in decode
  soc: qcom: smem: Fix incompatible types in comparison
  soc: qcom: ocmem: add missing clk_disable_unprepare() in ocmem_dev_probe()
  soc: qcom: socinfo: Add SoC ID for SM7125
  dt-bindings: arm: qcom,ids: Add SoC ID for SM7125
  dt-bindings: arm: qcom,ids: drop the IPQ5019 SoC ID
  soc: qcom: socinfo: drop the IPQ5019 SoC ID
  soc: qcom: socinfo: add SM4450 ID
  dt-bindings: arm: qcom,ids: add SoC ID for SM4450
  soc: qcom: pmic_glink: enable altmode for SM8550
  soc: qcom: pmic_glink_altmode: add retimer-switch support
  soc: qcom: pmic_glink_altmode: handle safe mode when disconnect
  soc: qcom: rpmhpd: Add SDX75 power domains
  dt-bindings: power: qcom,rpmpd: Add compatible for sdx75
  genpd: Makefile: build imx
  ...

Link: https://lore.kernel.org/r/20230818023338.2484467-1-andersson@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2023-08-21 21:11:55 -04:00
Etienne Carriere
fe95052fc7 dt-bindings: rcc: stm32: add STM32MP13 SCMI regulators IDs
Adds SCMI regulator identifiers for STM32MP13x family.

Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
Signed-off-by: Pascal Paillet <p.paillet@foss.st.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2023-08-16 10:58:41 +02:00
Robert Marko
268edfe96a dt-bindings: clock: qcom: ipq4019: add missing networking resets
Add bindings for the missing networking resets found in IPQ4019 GCC.

Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20230814104119.96858-1-robert.marko@sartura.hr
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-08-15 09:31:10 -07:00
Krzysztof Kozlowski
b3f9581aff dt-bindings: clock: samsung: remove define with number of clocks
Number of clocks supported by Linux drivers might vary - sometimes we
add new clocks, not exposed previously.  Therefore these numbers of
clocks should not be in the bindings, as that prevents changing them.
Remove it entirely from the bindings, once Linux drivers stopped using
them.

Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org>
Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com>
Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com>
Link: https://lore.kernel.org/r/20230808082738.122804-12-krzysztof.kozlowski@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2023-08-15 07:50:15 +02:00
Arnd Bergmann
99355a235a Merge tag 'ti-k3-dt-for-v6.6' of https://git.kernel.org/pub/scm/linux/kernel/git/ti/linux into soc/dt
TI K3 device tree updates for v6.6

New Boards:
 - TQ group's TQMaX4XxL AM64 SOM and MBaX4XxL carrier board
 - TI's AM62P5 Starter Kit (SK)

New features:
AM625:
 - Support for Display (parallel only) - hdmi+audio support for
   AM625-SK/BeaglePlay, TC358778 DPI to MIPI-DSI bridge support
   for verdin.
 - MCU MCAN support and enable of Toradex Verdin
 - Toradex Verdin Dahlia audio support
AM62A7:
 - MCU MCAN support
 - Enable USB Dual Role Device(DRD) support for AM62A7
   Starter Kit(SK).
AM64:
 - TQ group's tqma64xxl: Overlays for SD-card and wlan.
J721E:
 - Main domain CPSW9G and correponding gateway/ethernet
   switch expansion - GESI board.
J721S2/AM68:
 - New CAN instances, ehrpwm, Display (DSS) and am68-sk HDMI support
 - Main domain CPSW2G and correponding gateway/ethernet
   switch expansion - GESI board.
J784S4/AM69:
 - Boot phase tag marking in device tree
 - UFS support

Cleanups and non-urgent fixes:
 - Cosmetic style fixups around "=" and "{" whitespace usage.
 - Fixups across multiple SoCs/boards for pwm-tbclk to matchup with
   bindings
 - Serdes header file include/dt-bindings/mux/ti-serdes.h is now
   deprecated, use k3-serdes.h in soc dtsi folder.
 - All SoCs: Enable GPIO/SDHCI/OSPI/TSADC/C6/C7 DSP nodes at the
   board level.
 - Fixups for AM62: Crypto powerdomains are conditional to better
   represent control of the crypto engines by security controller.
 - Fixups for j721e: Duplicate wakeup_i2c node dropped for SoM board.
 - Fixups for j721s2/am68: pimux offsets for OSPI.
 - Fixups for j784s4/am69: Fixups for pinmux for ospi/adc interrupt
   ranges for wkup/main gpios

* tag 'ti-k3-dt-for-v6.6' of https://git.kernel.org/pub/scm/linux/kernel/git/ti/linux: (68 commits)
  arm64: dts: ti: verdin-am62: Add DSI display support
  arm64: dts: ti: Add support for the AM62P5 Starter Kit
  arm64: dts: ti: Introduce AM62P5 family of SoCs
  dt-bindings: arm: ti: Add bindings for AM62P5 SoCs
  arm64: dts: ti: k3-am69-sk: Add phase tags marking
  arm64: dts: ti: k3-j784s4-evm: Add phase tags marking
  arm64: dts: ti: k3-j784s4: Add phase tags marking
  arm64: dts: ti: k3-am625-beagleplay: Add HDMI support
  arm64: dts: ti: am62x-sk: Add overlay for HDMI audio
  arm64: dts: ti: k3-am62x-sk-common: Add HDMI support
  arm64: dts: ti: k3-am62-main: Add node for DSS
  arm64: dts: ti: k3-am62x-sk-common: Update main-i2c1 frequency
  arm64: dts: ti: k3-j721e: Enable C6x DSP nodes at the board level
  arm64: dts: ti: k3-j784s4: Enable C7x DSP nodes at the board level
  arm64: dts: ti: k3-j721e: Enable C7x DSP nodes at the board level
  arm64: dts: ti: k3-*: fix fss node dtbs check warnings
  arm64: dts: ti: k3-am64: Enable TSCADC nodes at the board level
  arm64: dts: ti: k3-am65: Enable TSCADC nodes at the board level
  arm64: dts: ti: k3-j721e: Enable TSCADC nodes at the board level
  arm64: dts: ti: k3-j7200: Enable GPIO nodes at the board level
  ...

Link: https://lore.kernel.org/r/20230814160651.frxohyshd2evp2k4@expenses
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2023-08-14 23:43:42 +02:00
Marco Felsch
35ec2abb54 dt-bindings: clocks: imx8mp: make sai4 a dummy clock
The hardware don't have a SAI4 instance so remove the define. Use a
comment to keep it as reference and to avoid confusion.

Fixes: 1088691447 ("dt-bindings: imx: Add clock binding doc for i.MX8MP")
Acked-by: Stephen Boyd <sboyd@kernel.org>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Marco Felsch <m.felsch@pengutronix.de>
Link: https://lore.kernel.org/r/20230731142150.3186650-2-m.felsch@pengutronix.de
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
2023-08-14 12:31:33 +03:00
Shengjiu Wang
a70cd8cdf7 dt-bindings: clock: fsl,imx8-acm: Add audio clock mux support
Add the clock dt-binding file for Audio Clock Mux. which
is the IP for i.MX8QM, i.MX8QXP, i.MX8DXL.

Add the clockid for clocks in header file.

The Audio Clock Mux is binded with all the audio IP and audio clocks
in the subsystem, so need to list the power domain of related clocks
and IPs. Each clock and IP has a power domain, so there are so many
power domains.

Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/1690260984-25744-2-git-send-email-shengjiu.wang@nxp.com
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
2023-08-14 12:27:52 +03:00
Otto Pflüger
593576a369 dt-bindings: clock: gcc-msm8917: Add definition for GPLL0_SLEEP_CLK_SRC
Add the missing #define for GPLL0_SLEEP_CLK_SRC, the parent clock of
GPLL0_EARLY.

Signed-off-by: Otto Pflüger <otto.pflueger@abscue.de>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20230802170317.205112-2-otto.pflueger@abscue.de
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-08-13 20:20:10 -07:00
Imran Shaik
df873243b2 dt-bindings: clock: Update GCC clocks for QDU1000 and QRU1000 SoCs
Add support for GCC_GPLL1_OUT_EVEN and GCC_DDRSS_ECPRI_GSI_CLK clock
bindings for QDU1000 and QRU1000 SoCs. While at it, update the
maintainers list.

Signed-off-by: Imran Shaik <quic_imrashai@quicinc.com>
Acked-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20230803105741.2292309-2-quic_imrashai@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-08-13 20:13:17 -07:00
Bjorn Andersson
9328ecb29d Merge branch '20230622-topic-8998clk-v2-1-6222fbc2916b@linaro.org' into arm64-for-6.6
Merge additional MSM8998 GCC DeviceTree binding constants for use in the
MSM8998 DeviceTree source.
2023-08-13 19:51:26 -07:00
Bjorn Andersson
9d1f3f343b Merge branch '20230622-topic-8998clk-v2-1-6222fbc2916b@linaro.org' into clk-for-6.6
Merge additional MSM8998 GCC DeviceTree binding constants through a
topic branch to make them available to the DeviceTree source tree as
well.
2023-08-13 19:49:57 -07:00
Konrad Dybcio
238e192bed dt-bindings: clk: qcom,gcc-msm8998: Add missing GPU/MMSS GPLL0 legs
GPLL0 has two separate outputs to both GPUSS and MMSS: one that's
2-divided and one that runs at the same rate as the GPLL0 itself.

Add the missing ones to the binding.

Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Jeffrey Hugo <quic_jhugo@quicinc.com>
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20230622-topic-8998clk-v2-1-6222fbc2916b@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-08-13 19:49:47 -07:00
Gokul krishna Krishnakumar
f9eac7e029 dt-bindings: firmware: qcom: scm: Updating VMID list
Adding the full list of VMID's, which are used by different clients to
pass to the secure world.

Signed-off-by: Gokul krishna Krishnakumar <quic_gokukris@quicinc.com>
Acked-by: Rob Herring <robh@kernel.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20230403204455.6758-1-quic_gokukris@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-08-11 13:10:59 -07:00
Bjorn Andersson
c02a547da3 Merge branch '1690533192-22220-2-git-send-email-quic_srichara@quicinc.com' into arm64-for-6.6
Merge the IPQ5018 GCC Devicetree binding through a topic branch, in
order to the the clock defines.
2023-08-11 10:51:15 -07:00
Bjorn Andersson
2f6be35d7c Merge branch '1690533192-22220-2-git-send-email-quic_srichara@quicinc.com' into clk-for-6.6
Merge the IPQ5018 GCC Devicetree binding through a topic branch, in
order to the the clock defines.
2023-08-11 10:50:07 -07:00
Sricharan Ramabadhran
f62d184ef7 dt-bindings: clock: Add IPQ5018 clock and reset
This patch adds support for the global clock controller found on
the IPQ5018 based devices.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Co-developed-by: Varadarajan Narayanan <quic_varada@quicinc.com>
Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
Signed-off-by: Sricharan Ramabadhran <quic_srichara@quicinc.com>
Link: https://lore.kernel.org/r/1690533192-22220-2-git-send-email-quic_srichara@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-08-11 10:46:59 -07:00
Neil Armstrong
40fb677285 dt-bindings: clk: axg-audio-clkc: expose all clock ids
Due to a policy change in clock ID bindings handling, expose
all the "private" clock IDs to the public clock dt-bindings
to move out of the previous maintenance scheme.

This refers to a discussion at [1] & [2] with Krzysztof about
the issue with the current maintenance.

It was decided to move every axg-audio-clkc ID to the public clock
dt-bindings headers to be merged in a single tree so we
can safely add new clocks without having merge issues.

[1] https://lore.kernel.org/all/c088e01c-0714-82be-8347-6140daf56640@linaro.org/
[2] https://lore.kernel.org/all/2fabe721-7434-43e7-bae5-088a42ba128d@app.fastmail.com/

Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20230607-topic-amlogic-upstream-clkid-public-migration-v2-14-38172d17c27a@linaro.org
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2023-08-08 16:06:17 +02:00
Neil Armstrong
09d65c0267 dt-bindings: clk: amlogic,a1-pll-clkc: expose all clock ids
Due to a policy change in clock ID bindings handling, expose
all the "private" clock IDs to the public clock dt-bindings
to move out of the previous maintenance scheme.

This refers to a discussion at [1] & [2] with Krzysztof about
the issue with the current maintenance.

It was decided to move every A1 pll ID to the public clock
dt-bindings headers to be merged in a single tree so we
can safely add new clocks without having merge issues.

[1] https://lore.kernel.org/all/c088e01c-0714-82be-8347-6140daf56640@linaro.org/
[2] https://lore.kernel.org/all/2fabe721-7434-43e7-bae5-088a42ba128d@app.fastmail.com/

Reviewed-by: Dmitry Rokosov <ddrokosov@sberdevices.ru>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20230607-topic-amlogic-upstream-clkid-public-migration-v2-13-38172d17c27a@linaro.org
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2023-08-08 16:06:17 +02:00
Neil Armstrong
57049a1cfc dt-bindings: clk: amlogic,a1-peripherals-clkc: expose all clock ids
Due to a policy change in clock ID bindings handling, expose
all the "private" clock IDs to the public clock dt-bindings
to move out of the previous maintenance scheme.

This refers to a discussion at [1] & [2] with Krzysztof about
the issue with the current maintenance.

It was decided to move every A1 peripherals ID to the public clock
dt-bindings headers to be merged in a single tree so we
can safely add new clocks without having merge issues.

[1] https://lore.kernel.org/all/c088e01c-0714-82be-8347-6140daf56640@linaro.org/
[2] https://lore.kernel.org/all/2fabe721-7434-43e7-bae5-088a42ba128d@app.fastmail.com/

Reviewed-by: Dmitry Rokosov <ddrokosov@sberdevices.ru>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20230607-topic-amlogic-upstream-clkid-public-migration-v2-12-38172d17c27a@linaro.org
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2023-08-08 16:06:17 +02:00
Neil Armstrong
165a194195 dt-bindings: clk: meson8b-clkc: expose all clock ids
Due to a policy change in clock ID bindings handling, expose
all the "private" clock IDs to the public clock dt-bindings
to move out of the previous maintenance scheme.

This refers to a discussion at [1] & [2] with Krzysztof about
the issue with the current maintenance.

It was decided to move every meson8b-clkc ID to the public clock
dt-bindings headers to be merged in a single tree so we
can safely add new clocks without having merge issues.

[1] https://lore.kernel.org/all/c088e01c-0714-82be-8347-6140daf56640@linaro.org/
[2] https://lore.kernel.org/all/2fabe721-7434-43e7-bae5-088a42ba128d@app.fastmail.com/

Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20230607-topic-amlogic-upstream-clkid-public-migration-v2-11-38172d17c27a@linaro.org
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2023-08-08 16:06:17 +02:00
Neil Armstrong
6655744d9a dt-bindings: clk: g12a-aoclkc: expose all clock ids
Due to a policy change in clock ID bindings handling, expose
all the "private" clock IDs to the public clock dt-bindings
to move out of the previous maintenance scheme.

This refers to a discussion at [1] & [2] with Krzysztof about
the issue with the current maintenance.

It was decided to move every g12a-aoclkc ID to the public clock
dt-bindings headers to be merged in a single tree so we
can safely add new clocks without having merge issues.

[1] https://lore.kernel.org/all/c088e01c-0714-82be-8347-6140daf56640@linaro.org/
[2] https://lore.kernel.org/all/2fabe721-7434-43e7-bae5-088a42ba128d@app.fastmail.com/

Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20230607-topic-amlogic-upstream-clkid-public-migration-v2-10-38172d17c27a@linaro.org
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2023-08-08 16:06:17 +02:00
Neil Armstrong
b1262497a2 dt-bindings: clk: g12a-clks: expose all clock ids
Due to a policy change in clock ID bindings handling, expose
all the "private" clock IDs to the public clock dt-bindings
to move out of the previous maintenance scheme.

This refers to a discussion at [1] & [2] with Krzysztof about
the issue with the current maintenance.

It was decided to move every g12a-clkc ID to the public clock
dt-bindings headers to be merged in a single tree so we
can safely add new clocks without having merge issues.

[1] https://lore.kernel.org/all/c088e01c-0714-82be-8347-6140daf56640@linaro.org/
[2] https://lore.kernel.org/all/2fabe721-7434-43e7-bae5-088a42ba128d@app.fastmail.com/

Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20230607-topic-amlogic-upstream-clkid-public-migration-v2-9-38172d17c27a@linaro.org
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2023-08-08 16:06:17 +02:00
Neil Armstrong
8fdbdc7918 dt-bindings: clk: axg-clkc: expose all clock ids
Due to a policy change in clock ID bindings handling, expose
all the "private" clock IDs to the public clock dt-bindings
to move out of the previous maintenance scheme.

This refers to a discussion at [1] & [2] with Krzysztof about
the issue with the current maintenance.

It was decided to move every axg-clkc ID to the public clock
dt-bindings headers to be merged in a single tree so we
can safely add new clocks without having merge issues.

[1] https://lore.kernel.org/all/c088e01c-0714-82be-8347-6140daf56640@linaro.org/
[2] https://lore.kernel.org/all/2fabe721-7434-43e7-bae5-088a42ba128d@app.fastmail.com/

Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20230607-topic-amlogic-upstream-clkid-public-migration-v2-8-38172d17c27a@linaro.org
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2023-08-08 16:06:17 +02:00
Neil Armstrong
9ce8555278 dt-bindings: clk: gxbb-clkc: expose all clock ids
Due to a policy change in clock ID bindings handling, expose
all the "private" clock IDs to the public clock dt-bindings
to move out of the previous maintenance scheme.

This refers to a discussion at [1] & [2] with Krzysztof about
the issue with the current maintenance.

It was decided to move every gxbb-clkc ID to the public clock
dt-bindings headers to be merged in a single tree so we
can safely add new clocks without having merge issues.

[1] https://lore.kernel.org/all/c088e01c-0714-82be-8347-6140daf56640@linaro.org/
[2] https://lore.kernel.org/all/2fabe721-7434-43e7-bae5-088a42ba128d@app.fastmail.com/

Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20230607-topic-amlogic-upstream-clkid-public-migration-v2-7-38172d17c27a@linaro.org
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2023-08-08 16:06:16 +02:00
Niravkumar L Rabara
d5f0942b50 dt-bindings: clock: add Intel Agilex5 clock manager
Add clock ID definitions for Intel Agilex5 SoCFPGA.
The registers in Agilex5 handling the clock is named as clock manager.

Signed-off-by: Teh Wen Ping <wen.ping.teh@intel.com>
Reviewed-by: Dinh Nguyen <dinguyen@kernel.org>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Niravkumar L Rabara <niravkumar.l.rabara@intel.com>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2023-08-08 06:32:34 -05:00
Niravkumar L Rabara
2a29fe831f dt-bindings: reset: add reset IDs for Agilex5
Add reset ID definitions required for Intel Agilex5 SoCFPGA, re-use
altr,rst-mgr-s10.h as common header file similar S10 & Agilex.

Acked-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Dinh Nguyen <dinguyen@kernel.org>
Signed-off-by: Niravkumar L Rabara <niravkumar.l.rabara@intel.com>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2023-08-08 06:32:34 -05:00
Huqiang Qin
0e8ec0226e dt-bindings: interrupt-controller: Add header file for Amlogic Meson-G12A SoCs
Add a new dt-binding header that details the interrupt number of the GPIO.

Signed-off-by: Huqiang Qin <huqiang.qin@amlogic.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20230724060108.1403662-2-huqiang.qin@amlogic.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-08-07 15:35:23 +02:00
Chengci.Xu
d5cda142d6 dt-bindings: mediatek: mt8188: Add binding for MM & INFRA IOMMU
Add descriptions for mt8188 IOMMU which also use ARM Short-Descriptor
translation table format.

In mt8188, there are two smi-common HW and IOMMU, one is for vdo(video
output), the other is for vpp(video processing pipe). They connects
with different smi-larbs, then some setting(larbid_remap) is different.
Differentiate them with the compatible string.

Something like this:

   IOMMU(VDO)          IOMMU(VPP)
      |                   |
 SMI_COMMON_VDO      SMI_COMMON_VPP
 ---------------     ----------------
  |     |    ...      |     |    ...
larb0 larb2  ...    larb1 larb3  ...

We also have an IOMMU that is for infra master like PCIe.
And infra master don't have the larb and ports.

Signed-off-by: Chengci.Xu <chengci.xu@mediatek.com>
Signed-off-by: Yong Wu <yong.wu@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20230602090227.7264-2-yong.wu@mediatek.com
Signed-off-by: Joerg Roedel <jroedel@suse.de>
2023-08-07 14:15:45 +02:00
David Wronek
b1b52717be dt-bindings: arm: qcom,ids: Add SoC ID for SM7125
Add the SoC ID for Qualcomm SM7125.

Signed-off-by: David Wronek <davidwronek@gmail.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20230723190725.1619193-3-davidwronek@gmail.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-07-31 16:28:43 -07:00
Kathiravan T
cb160cd7b1 dt-bindings: arm: qcom,ids: drop the IPQ5019 SoC ID
IPQ5019 SoC is never productized. So lets drop it.

Signed-off-by: Kathiravan T <quic_kathirav@quicinc.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20230724083745.1015321-3-quic_kathirav@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-07-31 16:28:20 -07:00
Tengfei Fan
4d641d2faf dt-bindings: arm: qcom,ids: add SoC ID for SM4450
Add the ID for the Qualcomm SM4450 SoC.

Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20230731080043.38552-6-quic_tengfan@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-07-31 16:25:22 -07:00
Dmitry Baryshkov
9f08d33496 dt-bindings: clock: drop qcom,lcc-mdm9615 header file
The header file for qcom,lcc-mdm9615 and qcom,lcc-msm8960 is the same
(as well as the drivers). Drop the qcom,lcc-mdm9615.h in favour of
qcom,lcc-msm8960.h

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20230512211727.3445575-3-dmitry.baryshkov@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-07-31 14:23:19 -07:00
Xianwei Zhao
83b03d6293 dt-bindings: power: add Amlogic C3 power domains
Add devicetree binding document and related header file for Amlogic C3 secure power domains.

Signed-off-by: Xianwei Zhao <xianwei.zhao@amlogic.com>
Acked-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20230707003710.2667989-3-xianwei.zhao@amlogic.com
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
2023-07-31 11:49:50 +02:00
Jayesh Choudhary
5438d75fb9 dt-bindings: ti-serdes-mux: Deprecate header with constants
The constants to define the idle state of SERDES MUX were defined in
bindings header. They are used only in DTS and driver uses the dt property
to set the idle state making it unsuitable for bindings.
The constants are moved to header next to DTS ("arch/arm64/boot/dts/ti/")
and all the references to bindings header are removed.
So add a warning to mark this bindings header as deprecated.

Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Acked-by: Roger Quadros <rogerq@kernel.org>
Acked-by: Peter Rosin <peda@axentia.se>
Link: https://lore.kernel.org/r/20230721125732.122421-3-j-choudhary@ti.com
Signed-off-by: Nishanth Menon <nm@ti.com>
2023-07-25 06:30:03 -05:00
Chancel Liu
2fe182dd27 dt-bindings: clock: imx93: Add PDM IPG clk
Add PDM IPG clk.

Reviewed-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Signed-off-by: Chancel Liu <chancel.liu@nxp.com>
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20230628061724.2056520-1-ping.bai@nxp.com
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
2023-07-25 10:28:42 +03:00
Huqiang Qin
e55ef16b84 dt-bindings: pinctrl: Add compatibles for Amlogic C3 SoCs
Add a new compatible name for Amlogic C3 pin controller, and add
a new dt-binding header file which document the detail pin names.

Signed-off-by: Huqiang Qin <huqiang.qin@amlogic.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20230714122441.3098337-2-huqiang.qin@amlogic.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-07-23 21:23:16 +02:00
Bjorn Andersson
ca32bd384e Merge branch '1689744162-9421-2-git-send-email-quic_rohiagar@quicinc.com' into arm64-for-6.6
Merge the new generic RPMHPD defines from a topic branch, to alow them
being used in DeviceTree source, and the driver.
2023-07-21 19:54:52 -07:00
Rohit Agarwal
7f31667d29 dt-bindings: power: qcom,rpmhpd: Add Generic RPMh PD indexes
Add Generic RPMh Power Domain indexes that can be used
for all the Qualcomm SoC henceforth.
The power domain indexes of these bindings are based on compatibility
with current targets like SM8[2345]50 targets.

Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com>
Suggested-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/1689744162-9421-2-git-send-email-quic_rohiagar@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-07-21 19:54:36 -07:00
Dmitry Baryshkov
b7297d4566 dt-bindings: iio: adc: qcom,spmi-adc7: use predefined channel ids
Each of qcom,spmi-adc7-pm*.h headers define a set of ADC channels that
can be used for monitoring on thie particular chip. Switch them to use
channel IDs defined in the dt-bindings/iio/qcom,spmi-vadc.h header
instead of specifying the numeric IDs.

Suggested-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20230707123027.1510723-2-dmitry.baryshkov@linaro.org
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
2023-07-20 19:21:30 +01:00
Dylan Hung
bbb8eb3cb0 dt-bindings: clock: ast2600: Add I3C and MAC reset definitions
Add reset definitions of AST2600 I3C and MAC controllers. In the case of
the I3C reset, since there is no reset-line hardware available for
`ASPEED_RESET_I3C_DMA`, a new macro `ASPEED_RESET_I3C` with the same ID
is introduced to provide a more accurate representation of the hardware.
The old macro `ASPEED_RESET_I3C_DMA` is kept to provide backward
compatibility.

Signed-off-by: Dylan Hung <dylan_hung@aspeedtech.com>
Link: https://lore.kernel.org/r/20230718062616.2822339-1-dylan_hung@aspeedtech.com
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-07-19 12:49:39 -07:00
Xingyu Wu
a097a5ec14 dt-bindings: clock: Add StarFive JH7110 Video-Output clock and reset generator
Add bindings for the Video-Output clock and reset generator (VOUTCRG)
on the JH7110 RISC-V SoC by StarFive Ltd.

Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2023-07-19 18:08:00 +01:00
Xingyu Wu
9b3938c0b8 dt-bindings: clock: Add StarFive JH7110 Image-Signal-Process clock and reset generator
Add bindings for the Image-Signal-Process clock and reset
generator (ISPCRG) on the JH7110 RISC-V SoC by StarFive Ltd.

Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2023-07-19 18:08:00 +01:00
Xingyu Wu
14b14a57e6 dt-bindings: clock: Add StarFive JH7110 System-Top-Group clock and reset generator
Add bindings for the System-Top-Group clock and reset generator (STGCRG)
on the JH7110 RISC-V SoC by StarFive Ltd.

Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2023-07-19 18:08:00 +01:00