Oak Zeng
062f380725
drm/amdgpu: Vega10 doorbell index initialization
...
v2: Use enum definition instead of hardcoded value
v3: Remove unused enum definition
Signed-off-by: Oak Zeng <ozeng@amd.com >
Suggested-by: Felix Kuehling <Felix.Kuehling@amd.com >
Suggested-by: Alex Deucher <alexander.deucher@amd.com >
Reviewed-by: Alex Deucher <alexander.deucher@amd.com >
Signed-off-by: Alex Deucher <alexander.deucher@amd.com >
2018-11-28 15:55:31 -05:00
Rex Zhu
73b1917454
drm/amdgpu: Add CLK IP base offset
...
so we can read/write the registers in CLK domain
through RREG32/WREG32_SOC15
Reviewed-by: Evan Quan <evan.quan@amd.com >
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com >
Signed-off-by: Alex Deucher <alexander.deucher@amd.com >
2018-07-10 14:16:39 -05:00
Evan Quan
1b59fb036a
drm/amdgpu: add MP1 and THM hw ip base reg offset
...
Signed-off-by: Evan Quan <evan.quan@amd.com >
Reviewed-by: Rex Zhu <Rex.Zhu@amd.com >
Signed-off-by: Alex Deucher <alexander.deucher@amd.com >
2018-04-11 13:14:01 -05:00
Hawking Zhang
f797dd5184
drm/amdgpu: include new ip and ip offset headers
...
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com >
Acked-by: Alex Deucher <alexander.deucher@amd.com >
Signed-off-by: Alex Deucher <alexander.deucher@amd.com >
2018-02-19 14:18:13 -05:00
Shaoyun Liu
4522824c48
drm/amdgpu: Dynamic initialize IP base offset
...
The base offsets of the IP blocks may change across
asics even though the relative register offsets
are the same for an IP. Handle this dynamically.
Acked-by: Christian Konig <christian.koenig@amd.com >
Signed-off-by: Shaoyun Liu <Shaoyun.Liu@amd.com >
Signed-off-by: Alex Deucher <alexander.deucher@amd.com >
2017-12-08 11:16:51 -05:00
