commit c8bcb01352 upstream.
While cdns_pcie_ep_set_msix() writes the Table Size field correctly (N-1),
the calculation of the PBA offset is wrong because it calculates space for
(N-1) entries instead of N.
This results in the following QEMU error when using PCI passthrough on a
device which relies on the PCI endpoint subsystem:
failed to add PCI capability 0x11[0x50]@0xb0: table & pba overlap, or they don't fit in BARs, or don't align
Fix the calculation of PBA offset in the MSI-X capability.
[bhelgaas: more specific subject and commit log]
Fixes: 3ef5d16f50 ("PCI: cadence: Add MSI-X support to Endpoint driver")
Signed-off-by: Niklas Cassel <cassel@kernel.org>
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Wilfred Mallawa <wilfred.mallawa@wdc.com>
Reviewed-by: Damien Le Moal <dlemoal@kernel.org>
Cc: stable@vger.kernel.org
Link: https://patch.msgid.link/20250514074313.283156-10-cassel@kernel.org
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
[ Upstream commit 8805f32a96 ]
If the call to pci_host_probe() in cdns_pcie_host_setup() fails, PM
runtime count is decremented in the error path using pm_runtime_put_sync().
But the runtime count is not incremented by this driver, but only by the
callers (cdns_plat_pcie_probe/j721e_pcie_probe). And the callers also
decrement the runtime PM count in their error path. So this leads to the
below warning from the PM core:
"runtime PM usage count underflow!"
So fix it by getting rid of pm_runtime_put_sync() in the error path and
directly return the errno.
Fixes: 49e427e6bd ("Merge branch 'pci/host-probe-refactor'")
Signed-off-by: Hans Zhang <18255117159@163.com>
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Link: https://patch.msgid.link/20250419133058.162048-1-18255117159@163.com
Signed-off-by: Sasha Levin <sashal@kernel.org>
commit d66b5b3362 upstream.
Commit e49ad66781 ("PCI: j721e: Add TI J784S4 PCIe configuration")
assigned the value of .linkdown_irq_regfield for the J784S4 SoC as the
"LINK_DOWN" macro corresponding to BIT(1), and as a result, the Link
Down interrupts on J784S4 SoC are missed.
According to the Technical Reference Manual and Register Documentation
for the J784S4 SoC[1], BIT(1) corresponds to "ENABLE_SYS_EN_PCIE_DPA_1",
which is not the correct field for the link-state interrupt. Instead, it
is BIT(10) of the "PCIE_INTD_ENABLE_REG_SYS_2" register that corresponds
to the link-state field named as "ENABLE_SYS_EN_PCIE_LINK_STATE".
Thus, set .linkdown_irq_regfield to the macro "J7200_LINK_DOWN", which
expands to BIT(10) and was first defined for the J7200 SoC. Other SoCs
already reuse this macro since it accurately represents the "link-state"
field in their respective "PCIE_INTD_ENABLE_REG_SYS_2" register.
1: https://www.ti.com/lit/zip/spruj52
Fixes: e49ad66781 ("PCI: j721e: Add TI J784S4 PCIe configuration")
Cc: stable@vger.kernel.org
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
[kwilczynski: commit log, add a missing .linkdown_irq_regfield member
set to the J7200_LINK_DOWN macro to struct j7200_pcie_ep_data]
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Link: https://lore.kernel.org/r/20250305132018.2260771-1-s-vadapalli@ti.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
[ Upstream commit 3ac47fbf4f ]
Per the Cadence's "PCIe Controller IP for AX14" user guide, Version
1.04, Section 9.1.7.1, "AXI Subordinate to PCIe Address Translation
Registers", Table 9.4, the bit 16 of the AXI Subordinate Address
(axi_s_awaddr) when set corresponds to MSG with data, and when not set,
to MSG without data.
However, the driver is currently doing the opposite and due to this,
the INTx is never received on the host.
So, fix the driver to reflect the documentation and also make INTx work.
Fixes: 37dddf14f1 ("PCI: cadence: Add EndPoint Controller driver for Cadence PCIe controller")
Signed-off-by: Hans Zhang <18255117159@163.com>
Signed-off-by: Hans Zhang <hans.zhang@cixtech.com>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Link: https://lore.kernel.org/r/20250214165724.184599-1-18255117159@163.com
[kwilczynski: commit log]
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
[ Upstream commit 22a9120479 ]
According to Section 2.2 of the PCI Express Card Electromechanical
Specification (Revision 5.1), in order to ensure that the power and the
reference clock are stable, PERST# has to be deasserted after a delay of
100 milliseconds (TPVPERL).
Currently, it is being assumed that the power is already stable, which
is not necessarily true.
Hence, change the delay to PCIE_T_PVPERL_MS to guarantee that power and
reference clock are stable.
Fixes: f3e25911a4 ("PCI: j721e: Add TI J721E PCIe driver")
Fixes: f96b697137 ("PCI: j721e: Use T_PERST_CLK_US macro")
Link: https://lore.kernel.org/r/20241104074420.1862932-1-s-vadapalli@ti.com
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
- Add DT "ti,syscon-acspcie-proxy-ctrl" and driver support to enable the
ACSPCIE module to drive Refclk for the Endpoint (Siddharth Vadapalli)
- Extract the cadence link setup from cdns_pcie_host_setup() so link setup
can be done separately during resume (Thomas Richard)
- Use dev_err_probe() to simplify j721e probe (Thomas Richard)
- Add T_PERST_CLK_US definition for the mandatory delay between Refclk
becoming stable and PERST# being deasserted (Thomas Richard)
- Add j721e suspend and resume support (Théo Lebrun)
* pci/controller/j721e:
PCI: j721e: Add suspend and resume support
PCI: j721e: Use T_PERST_CLK_US macro
PCI: Add T_PERST_CLK_US macro
PCI: j721e: Add reset GPIO to struct j721e_pcie
PCI: j721e: Use dev_err_probe() in the probe() function
PCI: cadence: Set cdns_pcie_host_init() global
PCI: cadence: Extract link setup sequence from cdns_pcie_host_setup()
PCI: j721e: Enable ACSPCIE Refclk if "ti,syscon-acspcie-proxy-ctrl" exists
dt-bindings: PCI: ti,j721e-pci-host: Add ACSPCIE proxy control property
Struct cdns_pcie_rc once had a .dev member, but it was removed by
bd22885aa1 ("PCI: cadence: Refactor driver to use as a core library").
Drop the extra kerneldoc for it.
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
The ACSPCIE module is capable of driving the reference clock required by
the PCIe Endpoint device. It is an alternative to on-board and external
reference clock generators. Enabling the output from the ACSPCIE module's
PAD IO Buffers requires clearing the "PAD IO disable" bits of the
ACSPCIE_PROXY_CTRL register in the CTRL_MMR register space.
Add support to enable the ACSPCIE reference clock output using the optional
device-tree property "ti,syscon-acspcie-proxy-ctrl".
Link: https://lore.kernel.org/linux-pci/20240829105316.1483684-3-s-vadapalli@ti.com
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
- Move DBI accesses from dw_pcie_ep_init() to dw_pcie_ep_init_complete() so
drivers for endpoints that require Refclk for DBI access, e.g., qcom and
tegra194, can control when this happens (Manivannan Sadhasivam)
- Add endpoint API kernel-doc (Manivannan Sadhasivam)
- Remove .deinit() callback and instead call rcar_gen4_pcie_ep_deinit()
explicitly from rcar-gen4, which was the only user (Manivannan
Sadhasivam)
- Rename dw_pcie_ep_exit() to dw_pcie_ep_deinit() to correspond with
dw_pcie_ep_init() (Manivannan Sadhasivam)
- Add dw_pcie_ep_cleanup() for drivers that need to clean up eDMA resources
when PERST# is asserted, e.g., qcom, tegra194 (Manivannan Sadhasivam)
- Rename dw_pcie_ep_init_complete() to dw_pcie_ep_init_registers() to
better reflect the functionality (Manivannan Sadhasivam)
- Call dw_pcie_ep_init_registers() directly from drivers instead of from
dw_pcie_ep_init() so drivers, e.g., qcom and tegra194, can do it when
Refclk is available (Manivannan Sadhasivam)
- Remove the "core_init_notifier" flag, which previously identified drivers
that required Refclk before DBI access, because it's now unnecessary
(Manivannan Sadhasivam)
* pci/controller/dwc:
PCI: endpoint: Remove "core_init_notifier" flag
PCI: dwc: ep: Call dw_pcie_ep_init_registers() API directly from all glue drivers
PCI: dwc: ep: Rename dw_pcie_ep_init_complete() to dw_pcie_ep_init_registers()
PCI: dwc: ep: Introduce dw_pcie_ep_cleanup() API for drivers supporting PERST#
PCI: dwc: ep: Rename dw_pcie_ep_exit() to dw_pcie_ep_deinit()
PCI: dwc: ep: Remove deinit() callback from struct dw_pcie_ep_ops
PCI: dwc: ep: Add Kernel-doc comments for APIs
PCI: dwc: ep: Fix DBI access failure for drivers requiring refclk from host
"core_init_notifier" flag is set by the glue drivers requiring refclk from
the host to complete the DWC core initialization. Also, those drivers will
send a notification to the EPF drivers once the initialization is fully
completed using the pci_epc_init_notify() API. Only then, the EPF drivers
will start functioning.
For the rest of the drivers generating refclk locally, EPF drivers will
start functioning post binding with them. EPF drivers rely on the
'core_init_notifier' flag to differentiate between the drivers.
Unfortunately, this creates two different flows for the EPF drivers.
So to avoid that, let's get rid of the "core_init_notifier" flag and follow
a single initialization flow for the EPF drivers. This is done by calling
the dw_pcie_ep_init_notify() from all glue drivers after the completion of
dw_pcie_ep_init_registers() API. This will allow all the glue drivers to
send the notification to the EPF drivers once the initialization is fully
completed.
Only difference here is that, the drivers requiring refclk from host will
send the notification once refclk is received, while others will send it
during probe time itself.
But this also requires the EPC core driver to deliver the notification
after EPF driver bind. Because, the glue driver can send the notification
before the EPF drivers bind() and in those cases the EPF drivers will miss
the event. To accommodate this, EPC core is now caching the state of the
EPC initialization in 'init_complete' flag and pci-ep-cfs driver sends the
notification to EPF drivers based on that after each EPF driver bind.
Link: https://lore.kernel.org/linux-pci/20240327-pci-dbi-rework-v12-8-082625472414@linaro.org
Tested-by: Niklas Cassel <cassel@kernel.org>
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Reviewed-by: Frank Li <Frank.Li@nxp.com>
Reviewed-by: Niklas Cassel <cassel@kernel.org>
Ever since commit f25b5fae29 ("PCI: endpoint: Setting a BAR size > 4 GB
is invalid if 64-bit flag is not set") it has been impossible to get the
.set_bar() callback with a BAR size > 2 GB (yes, 2GB!), if the BAR was
also not requested to be configured as a 64-bit BAR.
Thus, forcing setting the 64-bit flag for BARs larger than 2 GB in the
lower level driver is dead code and can be removed.
It is however possible that an EPF driver configures a BAR as 64-bit,
even if the requested size is < 4 GB.
Respect the requested BAR configuration, just like how it is already
respected with regards to the prefetchable bit.
Link: https://lore.kernel.org/linux-pci/20240320113157.322695-7-cassel@kernel.org
Signed-off-by: Niklas Cassel <cassel@kernel.org>
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
- Rename PCI_IRQ_LEGACY to PCI_IRQ_INTX to be more explicit and match spec
terminology (Bjorn Helgaas)
- Use existing PCI_IRQ_INTX, PCI_IRQ_MSI, PCI_IRQ_MSIX in artpec6, cadence,
designware, designware-plat, dra7xx, imx6, keembay, keystone, layerscape,
mhi, ntb, qcom, rcar, rcar-gen4, rockchip, tegra194, uniphier, vntb; drop
the redundant pci_epc_irq_type enum with the same values (Damien Le Moal)
- Use "intx" instead of "leg" or "legacy" when describing INTx interrupts
in endpoint core, endpoint tests, cadence, dra7xx, designware,
dw-rockchip, dwc core, imx6, keystone, layerscape, qcom, rcar-gen4,
rockchip, tegra194, uniphier, xilinx-nwl (Damien Le Moal)
* pci/irq-clean-up:
PCI: xilinx-nwl: Use INTX instead of legacy
PCI: rockchip-host: Rename rockchip_pcie_legacy_int_handler()
PCI: rockchip-ep: Use INTX instead of legacy
PCI: uniphier: Use INTX instead of legacy
PCI: tegra194: Use INTX instead of legacy
PCI: dw-rockchip: Rename rockchip_pcie_legacy_int_handler()
PCI: keystone: Use INTX instead of legacy
PCI: dwc: Rename dw_pcie_ep_raise_legacy_irq()
PCI: cadence: Use INTX instead of legacy
PCI: dra7xx: Rename dra7xx_pcie_raise_legacy_irq()
misc: pci_endpoint_test: Use INTX instead of LEGACY
PCI: endpoint: Rename LEGACY to INTX in test function driver
PCI: endpoint: Use INTX instead of legacy
PCI: endpoint: Drop PCI_EPC_IRQ_XXX definitions
PCI: Rename PCI_IRQ_LEGACY to PCI_IRQ_INTX
In the Cadence endpoint controller driver, rename the function
cdns_pcie_ep_send_legacy_irq() to cdns_pcie_ep_send_intx_irq() to match
the macro PCI_IRQ_INTX name. Related comments and messages mentioning
"legacy" are also changed to refer to "intx".
Link: https://lore.kernel.org/r/20231122060406.14695-9-dlemoal@kernel.org
Signed-off-by: Damien Le Moal <dlemoal@kernel.org>
Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org>
Reviewed-by: Christoph Hellwig <hch@lst.de>
- Use FIELD_GET()/FIELD_PREP() when possible throughout drivers/pci/ (Ilpo
Järvinen, Bjorn Helgaas)
- Rework DPC control programming for clarity (Ilpo Järvinen)
* pci/field-get:
PCI/portdrv: Use FIELD_GET()
PCI/VC: Use FIELD_GET()
PCI/PTM: Use FIELD_GET()
PCI/PME: Use FIELD_GET()
PCI/ATS: Use FIELD_GET()
PCI/ATS: Show PASID Capability register width in bitmasks
PCI: Use FIELD_GET() in Sapphire RX 5600 XT Pulse quirk
PCI: Use FIELD_GET()
PCI/MSI: Use FIELD_GET/PREP()
PCI/DPC: Use defines with DPC reason fields
PCI/DPC: Use defined fields with DPC_CTL register
PCI/DPC: Use FIELD_GET()
PCI: hotplug: Use FIELD_GET/PREP()
PCI: dwc: Use FIELD_GET/PREP()
PCI: cadence: Use FIELD_GET()
PCI: Use FIELD_GET() to extract Link Width
PCI: mvebu: Use FIELD_PREP() with Link Width
PCI: tegra194: Use FIELD_GET()/FIELD_PREP() with Link Width fields
# Conflicts:
# drivers/pci/controller/dwc/pcie-tegra194.c
The struct cdns_plat_pcie contains a member called is_rc that is not
being used beyond being assigned a value within the cdns_plat_pcie_probe()
function, which is then not used for anything.
Thus, drop is_rc from the struct cdns_plat_pcie, especially since there
already is an is_rc member within the struct cdns_plat_pcie_of_data that
is actively used to convey information about the PCIe controller mode.
[kwilczynski: commit log]
Signed-off-by: Li Chen <lchen@ambarella.com>
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
The DT of_device.h and of_platform.h date back to the separate
of_platform_bus_type before it as merged into the regular platform bus. As
part of that merge prepping Arm DT support 13 years ago, they "temporarily"
include each other. They also include platform_device.h and of.h. As a
result, there's a pretty much random mix of those include files used
throughout the tree. In order to detangle these headers and replace the
implicit includes with struct declarations, users need to explicitly
include the correct includes.
Link: https://lore.kernel.org/r/20230714174827.4061572-1-robh@kernel.org
Signed-off-by: Rob Herring <robh@kernel.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
The .remove() callback for a platform driver returns an int which makes
many driver authors wrongly assume it's possible to do error handling by
returning an error code. However the value returned is (mostly) ignored
and this typically results in resource leaks. To improve here there is a
quest to make the remove callback return void. In the first step of this
quest all drivers are converted to .remove_new() which already returns
void.
Trivially convert this driver from always returning zero in the remove
callback to the void returning variant.
[kwilczynski: commit log]
Link: https://lore.kernel.org/linux-pci/20230321193208.366561-6-u.kleine-koenig@pengutronix.de
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
The Link Retraining process is initiated to account for the Gen2 defect in
the Cadence PCIe controller in J721E SoC. The errata corresponding to this
is i2085, documented at:
https://www.ti.com/lit/er/sprz455c/sprz455c.pdf
The existing workaround implemented for the errata waits for the Data Link
initialization to complete and assumes that the link retraining process
at the Physical Layer has completed. However, it is possible that the
Physical Layer training might be ongoing as indicated by the
PCI_EXP_LNKSTA_LT bit in the PCI_EXP_LNKSTA register.
Fix the existing workaround, to ensure that the Physical Layer training
has also completed, in addition to the Data Link initialization.
Link: https://lore.kernel.org/r/20230315070800.1615527-1-s-vadapalli@ti.com
Fixes: 4740b969aa ("PCI: cadence: Retrain Link to work around Gen2 training defect")
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org>
Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
Replace SET_*_PM_OPS with *_PM_OPS, which which have the advantage that the
compiler always sees the PM callbacks as referenced, so they don't need to
be wrapped with "#ifdef CONFIG_PM_SLEEP" or tagged with "__maybe_unused" to
avoid "defined but not used" warnings.
See 1a3c7bb088 ("PM: core: Add new *_PM_OPS macros, deprecate old ones").
Link: https://lore.kernel.org/r/20220719215108.1583108-1-helgaas@kernel.org
Tested-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Pali Rohár <pali@kernel.org> # pci-mvebu.c
Reviewed-by: Arnd Bergmann <arnd@arndb.de>
Clear FLR (Function Level Reset) from device capabilities
registers for all physical functions.
During FLR, the Margining Lane Status and Margining Lane Control
registers should not be reset, as per PCIe specification.
However, the controller incorrectly resets these registers upon FLR.
This causes PCISIG compliance FLR test to fail. Hence preventing
all functions from advertising FLR support if flag quirk_disable_flr
is set.
Link: https://lore.kernel.org/r/1635165075-89864-1-git-send-email-pthombar@cadence.com
Signed-off-by: Parshuram Thombare <pthombar@cadence.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Christian reported a NULL pointer dereference in j721e_pcie_probe() caused
by 19e863828a ("PCI: j721e: Drop redundant struct device *"), which
removed struct j721e_pcie.dev since there's another copy in struct
cdns_pcie.dev reachable via j721e_pcie->cdns_pcie->dev.
The problem is that j721e_pcie->cdns_pcie was dereferenced before being
initialized:
j721e_pcie_probe
pcie = devm_kzalloc() # struct j721e_pcie
j721e_pcie_ctrl_init(pcie)
dev = pcie->cdns_pcie->dev <-- dereference cdns_pcie
switch (mode) {
case PCI_MODE_RC:
cdns_pcie = ... # alloc as part of pci_host_bridge
pcie->cdns_pcie = cdns_pcie <-- initialize pcie->cdns_pcie
Move the cdns_pcie initialization earlier so it is done before it is used.
This also simplifies the error exits.
Fixes: 19e863828a ("PCI: j721e: Drop redundant struct device *")
Link: https://lore.kernel.org/r/20220127222951.GA144828@bhelgaas
Link: https://lore.kernel.org/r/20220124122132.435743-1-christian.gmeiner@gmail.com
Reported-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Tested-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Fix a number of misspelled words, and while at it, correct two phrases used
to indicate a status of an operation where words used have been cleverly
truncated and thus always trigger a spellchecking error while performing a
static code analysis over the PCI tree.
[bhelgaas: reverse sense of quirk ternary]
Link: https://lore.kernel.org/r/20220107225942.121484-1-kw@linux.com
Signed-off-by: Krzysztof Wilczyński <kw@linux.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
- Add max-virtual-functions to endpoint binding (Kishon Vijay Abraham I)
- Add pci_epf_add_vepf() API to add virtual function to endpoint (Kishon
Vijay Abraham I)
- Add pci_epf_vepf_link() to link virtual function to endpoint physical
function (Kishon Vijay Abraham I)
- Add virtual function number to pci_epc_ops endpoint ops interfaces
(Kishon Vijay Abraham I)
- Simplify register base address computation for endpoint BAR configuration
(Kishon Vijay Abraham I)
- Add support to configure virtual functions in cadence endpoint driver
(Kishon Vijay Abraham I)
- Add SR-IOV configuration to endpoint test driver (Kishon Vijay Abraham I)
- Document configfs usage to create virtual functions for endpoints (Kishon
Vijay Abraham I)
* remotes/lorenzo/pci/endpoint:
Documentation: PCI: endpoint/pci-endpoint-cfs: Guide to use SR-IOV
misc: pci_endpoint_test: Populate sriov_configure ops to configure SR-IOV device
PCI: cadence: Add support to configure virtual functions
PCI: cadence: Simplify code to get register base address for configuring BAR
PCI: endpoint: Add virtual function number in pci_epc ops
PCI: endpoint: Add support to link a physical function to a virtual function
PCI: endpoint: Add support to add virtual function in endpoint core
dt-bindings: PCI: pci-ep: Add binding to specify virtual function
