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Author SHA1 Message Date
Shawn Guo
8ff9b9f4fb arm64: dts: qcom: sdm845: fix number of pins in 'gpio-ranges' 
[ Upstream commit 02058fc383 ]

The last cell of 'gpio-ranges' should be number of GPIO pins, and in
case of qcom platform it should match msm_pinctrl_soc_data.ngpio rather
than msm_pinctrl_soc_data.ngpio - 1.

This fixes the problem that when the last GPIO pin in the range is
configured with the following call sequence, it always fails with
-EPROBE_DEFER.

    pinctrl_gpio_set_config()
        pinctrl_get_device_gpio_range()
            pinctrl_match_gpio_range()

Fixes: bc2c806293 ("arm64: dts: qcom: sdm845: Add gpio-ranges to TLMM node")
Cc: Evan Green <evgreen@chromium.org>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Link: https://lore.kernel.org/r/20210303033106.549-2-shawn.guo@linaro.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
 2021-05-14 09:50:10 +02:00
Bjorn Andersson
4827f0cabc arm64: dts: qcom: sdm845: Limit ipa iommu streams 
[ Upstream commit 95e6f8467c ]

The Android and Windows firmware does not accept the use of 3 as a mask
to cover the IPA streams. But with 0x721 being related to WiFi and 0x723
being unsed the mapping can be reduced to just cover 0x720 and 0x722,
which is accepted.

Acked-by: Alex Elder <elder@linaro.org>
Tested-by: Alex Elder <elder@linaro.org>
Fixes: e9e89c45bf ("arm64: dts: sdm845: add IPA iommus property")
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20201123052305.157686-1-bjorn.andersson@linaro.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
 2020-12-30 11:53:21 +01:00
Linus Torvalds
e533cda12d Merge tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc 
Pull ARM Devicetree updates from Olof Johansson:
 "As usual, most of the changes are to devicetrees.

  Besides smaller fixes, some refactorings and cleanups, some of the new
  platforms and chips (or significant features) supported are below:

  Broadcom boards:
   - Cisco Meraki MR32 (BCM53016-based)
   - BCM2711 (RPi4) display pipeline support

  Actions Semi boards:
   - Caninos Loucos Labrador SBC (S500-based)
   - RoseapplePi SBC (S500-based)

  Allwinner SoCs/boards:
   - A100 SoC with Perf1 board
   - Mali, DMA, Cetrus and IR support for R40 SoC

  Amlogic boards:
   - Libretch S905x CC V2 board
   - Hardkernel ODROID-N2+ board

  Aspeed boards/platforms:
   - Wistron Mowgli (AST2500-based, Power9 OpenPower server)
   - Facebook Wedge400 (AST2500-based, ToR switch)

  Hisilicon SoC:
   - SD5203 SoC

  Nvidia boards:
   - Tegra234 VDK, for pre-silicon Orin SoC

  NXP i.MX boards:
   - Librem 5 phone
   - i.MX8MM DDR4 EVK
   - Variscite VAR-SOM-MX8MN SoM
   - Symphony board
   - Tolino Shine 2 HD
   - TQMa6 SoM
   - Y Soft IOTA Orion

  Rockchip boards:
   - NanoPi R2S board
   - A95X-Z2 board
   - more Rock-Pi4 variants

  STM32 boards:
   - Odyssey SOM board (STM32MP157CAC-based)
   - DH DRC02 board

  Toshiba SoCs/boards:
   - Visconti SoC and TPMV7708 board"

* tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (638 commits)
  ARM: dts: nspire: Fix SP804 users
  arm64: dts: lg: Fix SP804 users
  arm64: dts: lg: Fix SP805 clocks
  ARM: mstar: Fix up the fallout from moving the dts/dtsi files
  ARM: mstar: Add mstar prefix to all of the dtsi/dts files
  ARM: mstar: Add interrupt to pm_uart
  ARM: mstar: Add interrupt controller to base dtsi
  ARM: dts: meson8: remove two invalid interrupt lines from the GPU node
  arm64: dts: ti: k3-j7200-common-proc-board: Add USB support
  arm64: dts: ti: k3-j7200-common-proc-board: Configure the SERDES lane function
  arm64: dts: ti: k3-j7200-main: Add USB controller
  arm64: dts: ti: k3-j7200-main.dtsi: Add USB to SERDES lane MUX
  arm64: dts: ti: k3-j7200-main: Add SERDES lane control mux
  dt-bindings: ti-serdes-mux: Add defines for J7200 SoC
  ARM: dts: hisilicon: add SD5203 dts
  ARM: dts: hisilicon: fix the system controller compatible nodes
  arm64: dts: zynqmp: Fix leds subnode name for zcu100/ultra96 v1
  arm64: dts: zynqmp: Remove undocumented u-boot properties
  arm64: dts: zynqmp: Remove additional compatible string for i2c IPs
  arm64: dts: zynqmp: Rename buses to be align with simple-bus yaml
  ...
 2020-10-24 10:44:18 -07:00
Georgi Djakov
c8c61c09e3 arm64: dts: qcom: sdm845: Add interconnects property for display 
Add the interconnect paths that are used by the display (MDSS). This
will allow the driver to request the needed bandwidth and prevent
display flickering.

Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org>
Link: https://lore.kernel.org/r/20200915214511.786-1-georgi.djakov@linaro.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
 2020-09-15 23:45:22 +00:00
Georgi Djakov
7901c2bc3f arm64: dts: qcom: sdm845: Increase the number of interconnect cells 
Increase the number of interconnect-cells, as now we can include
the tag information. The consumers can specify the path tag as an
additional argument to the endpoints.

Tested-by: Sibi Sankar <sibis@codeaurora.org>
Reviewed-by: Sibi Sankar <sibis@codeaurora.org>
Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org>
Link: https://lore.kernel.org/r/20200903133134.17201-6-georgi.djakov@linaro.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
 2020-09-15 22:33:50 +00:00
Rajendra Nayak
e0b760a5f6 arm64: dts: sdm845: Fixup OPP table for all qup devices 
This OPP table was based on the clock VDD-FMAX tables seen in
downstream code, however it turns out the downstream clock
driver does update these tables based on later/production
rev of the chip and whats seen in the tables belongs to an
early engineering rev of the SoC.
Fix up the OPP tables such that it now matches with the
production rev of sdm845 SoC.

Tested-by: Amit Pundir <amit.pundir@linaro.org>
Tested-by: John Stultz <john.stultz@linaro.org>
Tested-by: Steev Klimaszewski <steev@kali.org>
Fixes: 13cadb34e5 ("arm64: dts: sdm845: Add OPP table for all qup devices")
Reported-by: John Stultz <john.stultz@linaro.org>
Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
Link: https://lore.kernel.org/r/1597227730-16477-1-git-send-email-rnayak@codeaurora.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
 2020-09-14 23:26:08 +00:00
Rajendra Nayak
137154871c arm64: dts: qcom: sdm845: Add OPP tables and power-domains for venus 
Add the OPP tables in order to be able to vote on the performance state of
a power-domain.

Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
Link: https://lore.kernel.org/r/1598970026-7199-5-git-send-email-rnayak@codeaurora.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
 2020-09-10 22:03:11 +00:00
Sharat Masetty
338bdbcc59 arm64: dts: qcom: SDM845: Enable GPU DDR bw scaling 
This patch adds the interconnects property for the gpu node and the
opp-peak-kBps property to the opps of the gpu opp table. This should
help enable DDR bandwidth scaling dynamically and proportionally to the
GPU frequency.

Signed-off-by: Sharat Masetty <smasetty@codeaurora.org>
Signed-off-by: Akhil P Oommen <akhilpo@codeaurora.org>
Link: https://lore.kernel.org/r/1594992579-20662-5-git-send-email-akhilpo@codeaurora.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
 2020-07-27 23:27:02 -07:00
Sai Prakash Ranjan
4a183020d3 arm64: dts: qcom: sdm845: Support ETMv4 power management 
Add "arm,coresight-loses-context-with-cpu" property to coresight
ETM nodes to avoid failure of trace session because of losing
context on entering deep idle states.

Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
Link: https://lore.kernel.org/r/20200721071343.2898-1-saiprakash.ranjan@codeaurora.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
 2020-07-21 21:36:21 -07:00
Rajendra Nayak
19ecbc8421 arm64: dts: sdm845: Add DSI and MDP OPP tables and power-domains 
Add the OPP tables for DSI and MDP based on the perf state/clk
requirements, and add the power-domains property to specify the
scalable power domain.

Tested-by: Rob Clark <robdclark@gmail.com>
Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
Link: https://lore.kernel.org/r/1594292674-15632-4-git-send-email-rnayak@codeaurora.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
 2020-07-17 13:22:35 -07:00
Eric Biggers
433f9a5729 arm64: dts: sdm845: add Inline Crypto Engine registers and clock 
Add the vendor-specific registers and clock for Qualcomm ICE (Inline
Crypto Engine) to the device tree node for the UFS host controller on
sdm845, so that the ufs-qcom driver will be able to use inline crypto.

Use a separate register range rather than extending the main UFS range
because there's a gap between the two, and the ICE registers are
vendor-specific.  (Actually, the hardware claims that the ICE range also
includes the array of standard crypto configuration registers; however,
on this SoC the Linux kernel isn't permitted to access them directly.)

Signed-off-by: Eric Biggers <ebiggers@google.com>
Link: https://lore.kernel.org/r/20200710072013.177481-4-ebiggers@kernel.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
 2020-07-14 13:01:01 -07:00
Rajendra Nayak
6123e7443f arm64: dts: sdm845: Add sdhc opps and power-domains 
Add the power domain supporting performance state and the corresponding
OPP tables for the sdhc device on sdm845.

Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
Link: https://lore.kernel.org/r/1593506712-24557-4-git-send-email-rnayak@codeaurora.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
 2020-07-13 16:43:47 -07:00
Rajendra Nayak
13cadb34e5 arm64: dts: sdm845: Add OPP table for all qup devices 
qup has a requirement to vote on the performance state of the CX domain
in sdm845 devices. Add OPP tables for these and also add power-domains
property for all qup instances for uart and spi.
i2c does not support scaling and uses a fixed clock.

Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
Signed-off-by: Stephen Boyd <swboyd@chromium.org>
Link: https://lore.kernel.org/r/1593506712-24557-2-git-send-email-rnayak@codeaurora.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
 2020-07-13 16:36:19 -07:00
Rajendra Nayak
5b4de2f8b5 arm64: dts: sdm845: Add qspi opps and power-domains 
Add the power domain supporting performance state and the corresponding
OPP tables for the qspi device on sdm845

Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
Link: https://lore.kernel.org/r/1593769293-6354-3-git-send-email-rnayak@codeaurora.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
 2020-07-13 16:16:08 -07:00
Sibi Sankar
54b50f2153 arm64: dts: qcom: sdm845: Add cpu OPP tables 
Add OPP tables required to scale DDR/L3 per freq-domain on SDM845 SoCs.

Tested-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
Link: https://lore.kernel.org/r/20200702204643.25785-1-sibis@codeaurora.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
 2020-07-09 07:45:44 -07:00
Bjorn Andersson
948f6161c6 arm64: dts: qcom: sdm845: Add IMEM and PIL info region 
Add a simple-mfd representing IMEM on SDM845 and define the PIL
relocation info region, so that post mortem tools will be able to locate
the loaded remoteprocs.

Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Reviewed-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20200622191942.255460-6-bjorn.andersson@linaro.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
 2020-07-01 22:10:44 -07:00
Linus Torvalds
e611c0fe31 Merge tag 'usb-5.8-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb 
Pull USB/PHY driver updates from Greg KH:
 "Here are the large set of USB and PHY driver updates for 5.8-rc1.

  Nothing huge, just lots of little things:

   - USB gadget fixes and additions all over the place

   - new PHY drivers

   - PHY driver fixes and updates

   - XHCI driver updates

   - musb driver updates

   - more USB-serial driver ids added

   - various USB quirks added

   - thunderbolt minor updates and fixes

   - typec updates and additions

  All of these have been in linux-next for a while with no reported
  issues"

* tag 'usb-5.8-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb: (245 commits)
  usb: dwc3: meson-g12a: fix USB2 PHY initialization on G12A and A1 SoCs
  usb: dwc3: meson-g12a: fix error path when fetching the reset line fails
  Revert "dt-bindings: usb: qcom,dwc3: Convert USB DWC3 bindings"
  Revert "dt-bindings: usb: qcom,dwc3: Add compatible for SC7180"
  Revert "dt-bindings: usb: qcom,dwc3: Introduce interconnect properties for Qualcomm DWC3 driver"
  USB: serial: ch341: fix lockup of devices with limited prescaler
  USB: serial: ch341: add basis for quirk detection
  CDC-ACM: heed quirk also in error handling
  USB: serial: option: add Telit LE910C1-EUX compositions
  usb: musb: Fix runtime PM imbalance on error
  usb: musb: jz4740: Prevent lockup when CONFIG_SMP is set
  usb: musb: mediatek: add reset FADDR to zero in reset interrupt handle
  usb: musb: use true for 'use_dma'
  usb: musb: start session in resume for host port
  usb: musb: return -ESHUTDOWN in urb when three-strikes error happened
  USB: serial: qcserial: add DW5816e QDL support
  thunderbolt: Add trivial .shutdown
  usb: dwc3: keystone: Turn on USB3 PHY before controller
  dt-bindings: usb: ti,keystone-dwc3.yaml: Add USB3.0 PHY property
  dt-bindings: usb: convert keystone-usb.txt to YAML
  ...
 2020-06-07 09:42:16 -07:00
Sandeep Maheswaram
11a8b115fe arm64: dts: qcom: sdm845: Add interconnect properties for USB 
Populate USB DT nodes with interconnect properties.

Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Signed-off-by: Sandeep Maheswaram <sanm@codeaurora.org>
Signed-off-by: Felipe Balbi <balbi@kernel.org>
 2020-05-25 11:09:42 +03:00
Alex Elder
e9e89c45bf arm64: dts: sdm845: add IPA iommus property 
Add an "iommus" property to the IPA node in "sdm845.dtsi".  It is
required because there are two regions of memory the IPA accesses
through an SMMU.  The next few patches define and map those regions.

Signed-off-by: Alex Elder <elder@linaro.org>
Link: https://lore.kernel.org/r/20200504181350.22822-1-elder@linaro.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
 2020-05-04 11:45:44 -07:00
Sandeep Maheswaram
d724b42ede arm64: dts: qcom: sdm845: Add generic QUSB2 V2 Phy compatible 
Use generic QUSB2 V2 Phy configuration for sdm845.

Signed-off-by: Sandeep Maheswaram <sanm@codeaurora.org>
Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/1583747589-17267-9-git-send-email-sanm@codeaurora.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
 2020-04-14 11:03:00 -07:00
Robert Foss
07484de372 arm64: dts: qcom: sdm845: Add i2c-qcom-cci node 
The sdm845 SOC ships with a CCI controller, which
has two CCI/I2C buses.

Signed-off-by: Robert Foss <robert.foss@linaro.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20200324155843.10719-4-robert.foss@linaro.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
 2020-04-13 22:04:48 -07:00
Alex Elder
392a585583 arm64: dts: sdm845: add IPA information 
Add IPA-related nodes and definitions to "sdm845.dtsi".

Signed-off-by: Alex Elder <elder@linaro.org>
Link: https://lore.kernel.org/r/20200313115237.10491-2-elder@linaro.org
[bjorn: Moved modem-init to cheza.dtsi]
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
 2020-03-16 22:16:35 -07:00
Srinivas Kandagatla
606057bd89 arm64: dts: qcom: sdm845: add pinctrl nodes for quat i2s 
Add pinctrl nodes required for QUAT I2S

Reviewed-by: Vinod Koul <vkoul@kernel.org>
Tested-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Link: https://lore.kernel.org/r/20200312143024.11059-5-srinivas.kandagatla@linaro.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
 2020-03-14 22:15:25 -07:00
Srinivas Kandagatla
3898fdc1c0 arm64: dts: qcom: sdm845: add apr nodes 
Reviewed-by: Vinod Koul <vkoul@kernel.org>
Tested-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Link: https://lore.kernel.org/r/20200312143024.11059-3-srinivas.kandagatla@linaro.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
 2020-03-14 22:13:38 -07:00
Srinivas Kandagatla
27ca1de07d arm64: dts: qcom: sdm845: add slimbus nodes 
Reviewed-by: Vinod Koul <vkoul@kernel.org>
Tested-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Link: https://lore.kernel.org/r/20200312143024.11059-2-srinivas.kandagatla@linaro.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
 2020-03-14 22:13:29 -07:00
Sibi Sankar
74f2659980 arm64: dts: qcom: sdm845: Add OSM L3 interconnect provider 
Add Operation State Manager (OSM) L3 interconnect provider on SDM845 SoCs.

Acked-by: Georgi Djakov <georgi.djakov@linaro.org>
Reviewed-by: Evan Green <evgreen@chromium.org>
Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
Link: https://lore.kernel.org/r/20200227105632.15041-7-sibis@codeaurora.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
 2020-03-05 21:45:27 -08:00
David Dai
b303f9f005 arm64: dts: sdm845: Redefine interconnect provider DT nodes 
Add the DT nodes for each of the Network-On-Chip interconnect
buses found on SDM845 based platform and redefine the rsc_hlos
child node as a bcm-voter device to better represent the hardware.

Reviewed-by: Evan Green <evgreen@chromium.org>
Acked-by: Georgi Djakov <georgi.djakov@linaro.org>
Signed-off-by: David Dai <daidavid1@codeaurora.org>
Signed-off-by: Odelu Kukatla <okukatla@codeaurora.org>
Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
Link: https://lore.kernel.org/r/20200209183411.17195-7-sibis@codeaurora.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
 2020-03-04 21:13:02 -08:00
Stanimir Varbanov
1222783ecf arm64: dts: sdm845: follow venus-sdm845v2 DT binding 
Move all pmdomain and clock resources to Venus DT node. And make
possible to support dynamic core assignment on v4.

Signed-off-by: Stanimir Varbanov <stanimir.varbanov@linaro.org>
Link: https://lore.kernel.org/r/20200106154929.4331-12-stanimir.varbanov@linaro.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
 2020-02-27 21:58:42 -08:00
Douglas Anderson
af85ef13a5 arm64: dts: qcom: sdm845: Add the missing clock on the videocc 
We're transitioning over to requiring the Qualcomm Video Clock
Controller to specify all the input clocks.  Let's add the one input
clock for the videocc for sdm845.

NOTE: Until the Linux driver for sdm845's video is updated, this clock
will not actually be used in Linux.  It will continue to use global
clock names to match things up.

Signed-off-by: Douglas Anderson <dianders@chromium.org>
Link: https://lore.kernel.org/r/20200203103049.v4.14.Id0599319487f075808baba7cba02c4c3c486dc80@changeid
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
 2020-02-24 21:02:32 -08:00
Douglas Anderson
bb2bd9bffb arm64: dts: qcom: sdm845: Add missing clocks / fix names on the gpucc 
We're transitioning over to requiring the Qualcomm GPU Clock
Controller to specify all the input clocks.  Let's add them for
sdm845.

As part of this we've decided that the xo clock should be referred to
in the bindings as "bi_tcxo".  Change the dts.

NOTE: Until the Linux driver for sdm845's gpucc is updated, these
clocks will not actually be used in Linux.  It will continue to use
global clock names to match things up.  Of course, Linux didn't use
the old "xo" clock anyway.

Signed-off-by: Douglas Anderson <dianders@chromium.org>
Link: https://lore.kernel.org/r/20200203103049.v4.8.If8596faf02408cef4bb9f52296b911eb9ba49287@changeid
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
 2020-02-24 21:02:30 -08:00
Douglas Anderson
0997882f96 arm64: dts: qcom: sdm845: Add the missing clocks on the dispcc 
We're transitioning over to requiring the Qualcomm Display Clock
Controller to specify all the input clocks.  Let's add them for
sdm845.

NOTES:
- Until the Linux driver for sdm845's dispcc is updated, these clocks
  will not actually be used in Linux.  It will continue to use global
  clock names to match things up.
- Although the clocks from the DP PHY are required, the DP PHY isn't
  represented in the dts yet.  Apparently the magic for this is just
  to use <0>.

Signed-off-by: Douglas Anderson <dianders@chromium.org>
Link: https://lore.kernel.org/r/20200203103049.v4.3.Ie80fa74e1774f4317d80d70d30ef4b78f16cc8df@changeid
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
 2020-02-24 21:02:28 -08:00
Alexandre Courbot
48a0585b53 arm64: dts: qcom: add Venus firmware node on Cheza 
Cheza boards require this node to probe, so add it.

Reviewed-by: Stanimir Varbanov <stanimir.varbanov@linaro.org>
Signed-off-by: Alexandre Courbot <acourbot@chromium.org>
Link: https://lore.kernel.org/r/20200108032623.113921-1-acourbot@chromium.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
 2020-02-24 20:51:23 -08:00
Bjorn Andersson
42ad231338 arm64: dts: qcom: sdm845: Add second PCIe PHY and controller 
Add the second PCIe controller and the associated QHP PHY found on
SDM845.

Tested-by: Julien Massot <jmassot@softbankrobotics.com>
Reviewed-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20191107002247.1127689-3-bjorn.andersson@linaro.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
 2020-02-24 16:11:18 -08:00
Bjorn Andersson
5c538e09cb arm64: dts: qcom: sdm845: Add first PCIe controller and PHY 
Add the GEN2 PCIe controller and PHY found on SDM845.

Tested-by: Julien Massot <jmassot@softbankrobotics.com>
Reviewed-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20191107002247.1127689-2-bjorn.andersson@linaro.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
 2020-02-24 16:11:05 -08:00
Rob Clark
f489b13dae arm64: dts: qcom: sdm845: move gpu zap nodes to per-device dts 
We want to specify per-device firmware-name, so move the zap node into
the .dts file for individual boards/devices.  This lets us get rid of
the /delete-node/ for cheza, which does not use zap.

Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Rob Clark <robdclark@chromium.org>
Link: https://lore.kernel.org/r/20200112195405.1132288-5-robdclark@gmail.com
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
 2020-01-13 11:45:51 -08:00
Vinod Koul
a8aa481a5d arm64: dts: qcom: sdm845: add the ufs reset 
Add the core UFS reset for sdm845

Signed-off-by: Vinod Koul <vkoul@kernel.org>
Link: https://lore.kernel.org/r/20200106070826.147064-4-vkoul@kernel.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
 2020-01-05 23:33:59 -08:00
Douglas Anderson
276bb28c29 arm64: dts: qcom: sdm845: Rename gic-its node to msi-controller 
This is just like commit ac00546a67 ("arm64: dts: qcom: sc7180:
Rename gic-its node to msi-controller") but for sdm845.  This fixes
all arm64/qcom device trees that I could find.

Reviewed-by: Rajendra Nayak <rnayak@codeaurora.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Link: https://lore.kernel.org/r/20191216222021.1.I684f124a05a1c3f0b113c8d06d5f9da5d69b801e@changeid
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
 2019-12-21 12:12:45 -08:00
Sai Prakash Ranjan
39abbd3087 arm64: dts: sdm845: Update the device tree node for LLCC 
LLCC cache-controller was renamed to system-cache-controller
to make schema pass the dt binding check. Update the device
tree node to reflect this change.

Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
Link: https://lore.kernel.org/r/a2bb92de65e90768bf1d6b8c0b7fbd43cba704d2.1573814758.git.saiprakash.ranjan@codeaurora.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
 2019-12-10 22:43:33 -08:00
Lina Iyer
aeae948f6a arm64: dts: qcom: setup PDC as the wakeup parent for TLMM on SDM845 
PDC always-on interrupt controller can detect certain GPIOs even when
the TLMM interrupt controller is powered off. Link the PDC as TLMM's
wakeup parent.

Signed-off-by: Lina Iyer <ilina@codeaurora.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Link: https://lore.kernel.org/r/1573855915-9841-12-git-send-email-ilina@codeaurora.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
 2019-12-10 09:42:01 -08:00
Lina Iyer
72b67ebf9d arm64: dts: qcom: add PDC interrupt controller for SDM845 
Add PDC interrupt controller device bindings for SDM845.

Signed-off-by: Lina Iyer <ilina@codeaurora.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Link: https://lore.kernel.org/r/1573855915-9841-11-git-send-email-ilina@codeaurora.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
 2019-12-10 09:42:01 -08:00
Amit Kucheria
e68ca6b6fd arm64: dts: sdm845: thermal: Add critical interrupt support 
Register critical interrupts for each of the two tsens controllers

Signed-off-by: Amit Kucheria <amit.kucheria@linaro.org>
Link: https://lore.kernel.org/r/c536e9cdb448bbad3441f6580fa57f1f921fb580.1573499020.git.amit.kucheria@linaro.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
 2019-12-10 09:41:55 -08:00
Rob Clark
43b0a4b482 arm64: dts: qcom: sdm845-cheza: delete zap-shader 
This is unused on cheza.  Delete the node to get ride of the reserved-
memory section, and to avoid the driver from attempting to load a zap
shader that doesn't exist every time it powers up the GPU.

This also avoids a massive amount of dmesg spam about missing zap fw:
  msm ae00000.mdss: [drm:adreno_request_fw] *ERROR* failed to load
qcom/a630_zap.mdt: -2
  adreno 5000000.gpu: [drm:adreno_zap_shader_load] *ERROR* Unable to
load a630_zap.mdt

Signed-off-by: Rob Clark <robdclark@chromium.org>
Cc: Douglas Anderson <dianders@chromium.org>
Fixes: 3fdeaee951 ("arm64: dts: sdm845: Add zap shader region for GPU")
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Tested-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Andy Gross <agross@kernel.org>
 2019-10-27 00:39:01 -05:00
Amit Kucheria
4fc5d78fda arm64: dts: sdm845: thermal: Add interrupt support 
Register upper-lower interrupts for each of the two tsens controllers.

Signed-off-by: Amit Kucheria <amit.kucheria@linaro.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Signed-off-by: Andy Gross <agross@kernel.org>
 2019-10-27 00:05:38 -05:00
Bjorn Andersson
ef8576789e arm64: dts: qcom: sdm845: Add APSS watchdog node 
Add a node describing the watchdog found in the application subsystem.

Reviewed-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
 2019-10-20 18:59:03 -07:00
Vinod Koul
1dd70853f8 arm64: dts: sdm845: Add parent clock for rpmhcc 
RPM clock controller has parent as xo, so specify that in DT node for
rpmhcc

Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
 2019-08-26 17:43:23 -07:00
Srinivas Kandagatla
b4d08173bf arm64: sdm845: add adsp and cdsp fastrpc nodes 
Add fastrpc compute context bank nodes to both cdsp and adsp.

Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
 2019-08-21 10:47:47 -07:00
Matthias Kaehlcke
d4507d4213 arm64: dts: sdm845: Add dynamic CPU power coefficients 
Add dynamic power coefficients for the Silver and Gold CPU cores of
the Qualcomm SDM845.

Signed-off-by: Matthias Kaehlcke <mka@chromium.org>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Reviewed-by: Amit Kucheria <amit.kucheria@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
 2019-08-19 22:25:02 -07:00
Thara Gopinath
7e4b5f241a arm64: dts: qcom: Extend AOSS QMP node 
AOSS hosts resources that can be used to warm up the SoC.
Add nodes for these resources.

Signed-off-by: Thara Gopinath <thara.gopinath@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
 2019-08-05 15:11:38 -07:00
Sai Prakash Ranjan
ed7d6110c1 arm64: dts: qcom: sdm845: Add Coresight support 
Add coresight components found on Qualcomm SDM845 SoC.

Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Acked-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
 2019-08-05 15:10:02 -07:00
Sai Prakash Ranjan
ba0411ddd1 arm64: dts: sdm845: Add device node for Last level cache controller 
Last level cache (aka. system cache) controller provides control
over the last level cache present on SDM845. This cache lies after
the memory noc, right before the DDR.

Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
Signed-off-by: Vivek Gautam <vivek.gautam@codeaurora.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
 2019-08-05 14:48:56 -07:00