raspi/linux
1
0
Fork 1
mirror of https://github.com/raspberrypi/linux.git synced 2025-12-24 19:12:14 +00:00
Code Issues Projects Releases Wiki Activity
1,153,513 Commits 105 Branches 108 Tags
e8254a8ec901b78d939d8ab11a56bc98eb7862db
Commit Graph

27 Commits

Author SHA1 Message Date
Krzysztof Kozlowski
9b4dc87d35 ARM: dts: qcom: sdx65: add dedicated IMEM and syscon compatibles 
Add proper compatibles to the IMEM device node:
1. syscon as required by the bindings, even though it is not currently
   used,
2. dedicated compatible as required for syscon and simple-mfd nodes.

Align the node name to match IMEM type of device - SRAM.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221104190840.134733-2-krzysztof.kozlowski@linaro.org
 2022-11-06 21:09:03 -06:00
Krzysztof Kozlowski
5eb82ddb72 ARM: dts: qcom: align SDHCI reg-names with DT schema 
DT schema requires SDHCI reg names to be hc/core without "_mem" suffix,
just like TXT bindings were expecting before the conversion.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20220712144245.17417-5-krzysztof.kozlowski@linaro.org
 2022-09-13 22:11:30 -05:00
Johan Hovold
079926b5a2 ARM: dts: qcom: sdx65: reorder USB interrupts 
Three SoCs did not follow the interrupt order specified by the USB
controller binding.

While keeping the non-SuperSpeed interrupts together seems natural,
reorder the interrupts to match the binding.

Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
[bjorn: Split out from arm64 patch]
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220715070248.19078-5-johan+linaro@kernel.org
 2022-07-16 21:31:56 -05:00
Bhupesh Sharma
2477d81901 ARM: dts: qcom: Fix sdhci node names - use 'mmc@' 
Since the Qualcomm sdhci-msm device-tree binding has been converted
to yaml format, 'make dtbs_check' reports issues with
inconsistent 'sdhci@' convention used for specifying the
sdhci nodes. The generic mmc bindings expect 'mmc@' format
instead.

Fix the same.

Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
Cc: Rob Herring <robh@kernel.org>
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
[bjorn: Extracted from combined arm64 patch]
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220514215424.1007718-2-bhupesh.sharma@linaro.org
 2022-07-02 22:20:56 -05:00
Rohit Agarwal
39eebfce4b ARM: dts: qcom: sdx65: Add Watchdog support 
Enable Watchdog support for Application Processor Subsystem (APSS) block
on SDX65 platform.

Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/1654080312-5408-11-git-send-email-quic_rohiagar@quicinc.com
 2022-06-27 16:12:04 -05:00
Rohit Agarwal
df6d7b86f4 ARM: dts: qcom: sdx65: Add pshold support 
Add support for pshold block to drive pshold towards the PMIC, which is
used to trigger a configurable event such as reboot or poweroff of the
SDX65 platform.

Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/1654080312-5408-12-git-send-email-quic_rohiagar@quicinc.com
 2022-06-27 16:10:59 -05:00
Rohit Agarwal
a3ae01ed96 ARM: dts: qcom: sdx65: Add Modem remoteproc node 
Add modem support to SDX65 using the PAS remoteproc driver.

Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/1654080312-5408-7-git-send-email-quic_rohiagar@quicinc.com
 2022-06-27 16:10:58 -05:00
Rohit Agarwal
261e09b4e3 ARM: dts: qcom: sdx65: Add SCM node 
Add SCM node to enable SCM functionality on SDX65 platform.

Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/1654080312-5408-6-git-send-email-quic_rohiagar@quicinc.com
 2022-06-27 16:10:58 -05:00
Rohit Agarwal
69117a2abf ARM: dts: qcom: sdx65: Add IMEM and PIL info region 
Add a simple-mfd representing IMEM on SDX65 and define the PIL
relocation info region, so that post mortem tools will be able to locate
the loaded remoteproc.

Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/1654080312-5408-4-git-send-email-quic_rohiagar@quicinc.com
 2022-06-27 16:10:34 -05:00
Rohit Agarwal
7f928c7358 ARM: dts: qcom: sdx65: Add modem SMP2P node 
Add SMP2P nodes for the SDX65 platform to communicate with the modem.

Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/1654080312-5408-3-git-send-email-quic_rohiagar@quicinc.com
 2022-06-27 16:10:34 -05:00
Rohit Agarwal
b427679adc ARM: dts: qcom: sdx65: Add CPUFreq support 
Add CPUFreq support to SDX65 platform using the cpufreq-dt driver.
There is no dedicated hardware block available on this platform to
carry on the CPUFreq duties. Hence, it is accomplished using the CPU
clock and regulators tied together by the operating points table.

Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/1654080312-5408-2-git-send-email-quic_rohiagar@quicinc.com
 2022-06-27 16:10:33 -05:00
Kaushal Kumar
0ec15b6f76 ARM: dts: qcom: sdx65: Add QPIC NAND support 
Add devicetree node to enable support for QPIC
NAND controller on Qualcomm SDX65 platform.
Since there is no "aon" clock in SDX65, a dummy
clock is provided.

Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Kaushal Kumar <quic_kaushalk@quicinc.com>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/1651511286-18690-3-git-send-email-quic_kaushalk@quicinc.com
 2022-06-27 16:08:49 -05:00
Kaushal Kumar
ab11b74d87 ARM: dts: qcom: sdx65: Add QPIC BAM support 
Add devicetree node to enable support for QPIC
BAM DMA controller on Qualcomm SDX65 platform.

Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Kaushal Kumar <quic_kaushalk@quicinc.com>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/1651511286-18690-2-git-send-email-quic_kaushalk@quicinc.com
 2022-06-27 16:08:49 -05:00
Rohit Agarwal
fbb6447deb ARM: dts: qcom: sdx65: Add USB3 and PHY support 
Add devicetree nodes for enabling USB3 controller, Qcom QMP PHY and
SNPS HS PHY on SDX65.

Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/1651482395-29443-4-git-send-email-quic_rohiagar@quicinc.com
 2022-06-27 16:08:03 -05:00
Rohit Agarwal
b456b5e7d1 ARM: dts: qcom: sdx65: Add interconnect nodes 
Add interconnect devicetree nodes in SDX65 platform.

Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
[bjorn: Sorted nodes]
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/1651482395-29443-2-git-send-email-quic_rohiagar@quicinc.com
 2022-06-27 16:07:55 -05:00
Rohit Agarwal
e378b96533 ARM: dts: qcom: sdx65: Add Shared memory manager support 
Add smem node to support shared memory manager on SDX65 platform.

Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/1651480665-14978-5-git-send-email-quic_rohiagar@quicinc.com
 2022-06-27 16:02:11 -05:00
Krzysztof Kozlowski
97c246c825 ARM: dts: qcom: sdx55: remove wrong unit address from RPMH RSC clocks 
The clock controller of RPMH RSC does not have 'reg' property, so should
not have unit address.

Fixes: bae2f5979c ("ARM: dts: qcom: Add SDX65 platform and MTP board support")
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220411085935.130072-2-krzysztof.kozlowski@linaro.org
 2022-04-19 12:25:08 -05:00
Rohit Agarwal
78254f3b7d ARM: dts: qcom: sdx65: Add support for TCSR Mutex 
Add TCSR Mutex node to support Qualcomm Hardware Mutex block
on SDX65 platform.

Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/1649670615-21268-7-git-send-email-quic_rohiagar@quicinc.com
 2022-04-12 22:35:06 -05:00
Rohit Agarwal
98187f7b74 ARM: dts: qcom: sdx65: Enable ARM SMMU 
Add a node for the ARM SMMU found in the SDX65.

Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/1649670615-21268-6-git-send-email-quic_rohiagar@quicinc.com
 2022-04-12 22:35:05 -05:00
Rohit Agarwal
dc1a380fcb ARM: dts: qcom: sdx65: Add support for SDHCI controller 
Add devicetree support for SDHCI controller found in Qualcomm SDX65
platform. The SDHCI controller is based on the MSM SDHCI v5 IP.

Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/1649670615-21268-4-git-send-email-quic_rohiagar@quicinc.com
 2022-04-12 22:35:05 -05:00
Rohit Agarwal
a30be44449 ARM: dts: qcom: sdx65: Add reserved memory nodes 
Add reserved memory nodes to the SDX65 dtsi as defined by
the memory map.

Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/1649670615-21268-2-git-send-email-quic_rohiagar@quicinc.com
 2022-04-12 22:35:04 -05:00
Rohit Agarwal
52fedb2f32 ARM: dts: qcom: sdx65: Add rpmpd node 
Add rpmpd node and opps for this node to the SDX65 dts.

Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/1647411447-25249-5-git-send-email-quic_rohiagar@quicinc.com
 2022-04-12 22:29:40 -05:00
Rohit Agarwal
324db76df1 ARM: dts: qcom: sdx65: Add spmi node 
Add SPMI node to SDX65 dtsi.

Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/1647411447-25249-2-git-send-email-quic_rohiagar@quicinc.com
 2022-04-12 21:55:37 -05:00
Rohit Agarwal
ce91bc005e ARM: dts: qcom: sdx65: Add support for APCS block 
The APCS block on SDX65 acts as a mailbox controller and also provides
clock output for the Cortex A7 CPU.

Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/1645505785-2271-5-git-send-email-quic_rohiagar@quicinc.com
 2022-04-12 21:22:34 -05:00
Rohit Agarwal
02c5553523 ARM: dts: qcom: sdx65: Add support for A7 PLL clock 
On SDX65 there is a separate A7 PLL which is used to provide high
frequency clock to the Cortex A7 CPU via a MUX.

Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/1645505785-2271-4-git-send-email-quic_rohiagar@quicinc.com
 2022-04-12 21:22:26 -05:00
Vamsi krishna Lanka
ff8b573a6c ARM: dts: qcom: sdx65: Add pincontrol node 
This commit adds pincontrol node to SDX65 dts.

Signed-off-by: Vamsi Krishna Lanka <quic_vamslank@quicinc.com>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/1635552125-16407-4-git-send-email-quic_vamslank@quicinc.com
 2021-12-14 21:04:33 -06:00
Vamsi krishna Lanka
bae2f5979c ARM: dts: qcom: Add SDX65 platform and MTP board support 
Add basic devicetree support for SDX65 platform and MTP board from
Qualcomm. The SDX65 platform features an ARM Cortex A7 CPU which forms
the Application Processor Sub System (APSS) along with standard Qualcomm
peripherals like GCC, TLMM, BLSP, QPIC, and BAM etc... Also, there
exists the networking parts such as IPA, MHI, PCIE-EP, EMAC, and Modem
etc..

This commit adds basic devicetree support that includes GCC, RPMh clock, INTC
and Debug UART.

Signed-off-by: Vamsi Krishna Lanka <quic_vamslank@quicinc.com>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/1635552125-16407-3-git-send-email-quic_vamslank@quicinc.com
 2021-12-14 21:04:33 -06:00