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696b47f656
RP1 exposes GPIOs. Add a pinctrl driver to allow control of those.
Signed-off-by: Phil Elwell <phil@raspberrypi.com>
pinctrl: rp1: Use the correct per-bank GPIO base
The GPIO start for each bank - min_gpio - must be used in the IRQ
handler.
Signed-off-by: Phil Elwell <phil@raspberrypi.com>
pinctrl: rp1: Allow legacy brcm,pins on all banks
Support the use of the brcm,pins property for GPIOs in banks 1 and 2,
but only for inputs and outputs - no other legacy mapping.
Signed-off-by: Phil Elwell <phil@raspberrypi.com>
pinctrl: rp1: Support interrupt CPU affinity
See: https://github.com/raspberrypi/linux/issues/6077
Signed-off-by: Phil Elwell <phil@raspberrypi.com>
pinctrl: rp1: Clear events when setting IRQ type
When setting the interrupt type, it is unlikely that any latched events
are of interest, so clear them.
Signed-off-by: Phil Elwell <phil@raspberrypi.com>
pinctrl: rp1: Add strict_gpiod module parameter
Setting strict_gpiod to Y makes libgpiod and the gpiod utilities behave
as documented, i.e. pins are returned to being GPIO inputs when they are
released.
Signed-off-by: Phil Elwell <phil@raspberrypi.com>
pinctrl: rp1: Use persist_gpio_outputs
Following 8ff05989b4, adopt the same
parameter name but with the opposite default.
Signed-off-by: Phil Elwell <phil@raspberrypi.com>
pinctrl: rp1: jump through hoops to avoid PCIe latency issues
Automatic link power saving plus the ability of a root complex to buffer
pending posted write transfers (and consider them complete before being
transmitted on the wire) causes compression of updates to GPIO state.
The large bandwidth of a Gen 2 x4 link means the writes toggle state
inside RP1 as fast as it can go (~20MHz), which is bad for applications
wanting bitbash with at least a few microseconds of delay between
updates.
By tailoring IO access patterns to a special Root Complex register,
writes to GPIOs can be stalled until the link wakes - meaning all writes
end up with a reasonably consistent minimum pacing (~200ns).
Additionally, write barriers have no effect other than to arbitrarily
delay some writes by a small, variable amount - so remove the vast
majority of these in areas that could be hot-paths.
Although the IO memory is mapped with Device strongly-ordered semantics,
this doesn't prevent the splitter inside BCM2712 from letting an MMIO
read request to a GPIO register get ahead of the pacing writes to the
Root Complex register. So each pin state read must flush writes out to
the Outer-Shareable domain.
Signed-off-by: Jonathan Bell <jonathan@raspberrypi.com>