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8271eb9ffa
commitbdae73cd37upstream. As of commitb9d4d42ad9(ARM: Remove __ARCH_WANT_INTERRUPTS_ON_CTXSW on pre-ARMv6 CPUs), the mm switching on VIVT processors is done in the finish_arch_post_lock_switch() function to avoid whole cache flushing with interrupts disabled. The need for deferred mm switch is stored as a thread flag (TIF_SWITCH_MM). However, with preemption enabled, we can have another thread switch before finish_arch_post_lock_switch(). If the new thread has the same mm as the previous 'next' thread, the scheduler will not call switch_mm() and the TIF_SWITCH_MM flag won't be set for the new thread. This patch moves the switch pending flag to the mm_context_t structure since this is specific to the mm rather than thread. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Reported-by: Marc Kleine-Budde <mkl@pengutronix.de> Tested-by: Marc Kleine-Budde <mkl@pengutronix.de> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
38 lines
631 B
C
38 lines
631 B
C
#ifndef __ARM_MMU_H
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#define __ARM_MMU_H
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#ifdef CONFIG_MMU
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typedef struct {
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#ifdef CONFIG_CPU_HAS_ASID
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atomic64_t id;
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#else
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int switch_pending;
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#endif
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unsigned int vmalloc_seq;
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unsigned long sigpage;
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} mm_context_t;
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#ifdef CONFIG_CPU_HAS_ASID
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#define ASID_BITS 8
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#define ASID_MASK ((~0ULL) << ASID_BITS)
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#define ASID(mm) ((mm)->context.id.counter & ~ASID_MASK)
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#else
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#define ASID(mm) (0)
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#endif
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#else
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/*
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* From nommu.h:
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* Copyright (C) 2002, David McCullough <davidm@snapgear.com>
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* modified for 2.6 by Hyok S. Choi <hyok.choi@samsung.com>
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*/
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typedef struct {
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unsigned long end_brk;
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} mm_context_t;
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#endif
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#endif
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