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0a4b61d9c2
Recent AMD node rework removed the "search and count" method of caching AMD
root devices. This depended on the value from a Data Fabric register that was
expected to hold the PCI bus of one of the root devices attached to that
fabric.
However, this expectation is incorrect. The register, when read from PCI
config space, returns the bitwise-OR of the buses of all attached root
devices.
This behavior is benign on AMD reference design boards, since the bus numbers
are aligned. This results in a bitwise-OR value matching one of the buses. For
example, 0x00 | 0x40 | 0xA0 | 0xE0 = 0xE0.
This behavior breaks on boards where the bus numbers are not exactly aligned.
For example, 0x00 | 0x07 | 0xE0 | 0x15 = 0x1F.
The examples above are for AMD node 0. The first root device on other nodes
will not be 0x00. The first root device for other nodes will depend on the
total number of root devices, the system topology, and the specific PCI bus
number assignment.
For example, a system with 2 AMD nodes could have this:
Node 0 : 0x00 0x07 0x0e 0x15
Node 1 : 0x1c 0x23 0x2a 0x31
The bus numbering style in the reference boards is not a requirement. The
numbering found in other boards is not incorrect. Therefore, the root device
caching method needs to be adjusted.
Go back to the "search and count" method used before the recent rework.
Search for root devices using PCI class code rather than fixed PCI IDs.
This keeps the goal of the rework (remove dependency on PCI IDs) while being
able to support various board designs.
Merge helper functions to reduce code duplication.
[ bp: Reflow comment. ]
Fixes: 40a5f6ffdf ("x86/amd_nb: Simplify root device search")
Signed-off-by: Yazen Ghannam <yazen.ghannam@amd.com>
Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de>
Cc: stable@vger.kernel.org
Link: https://patch.msgid.link/all/20251028-fix-amd-root-v2-1-843e38f8be2c@amd.com
60 lines
1.5 KiB
C
60 lines
1.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* AMD Node helper functions and common defines
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*
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* Copyright (c) 2024, Advanced Micro Devices, Inc.
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* All Rights Reserved.
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*
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* Author: Yazen Ghannam <Yazen.Ghannam@amd.com>
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*
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* Note:
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* Items in this file may only be used in a single place.
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* However, it's prudent to keep all AMD Node functionality
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* in a unified place rather than spreading throughout the
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* kernel.
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*/
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#ifndef _ASM_X86_AMD_NODE_H_
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#define _ASM_X86_AMD_NODE_H_
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#include <linux/pci.h>
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#define MAX_AMD_NUM_NODES 8
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#define AMD_NODE0_PCI_SLOT 0x18
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struct pci_dev *amd_node_get_func(u16 node, u8 func);
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static inline u16 amd_num_nodes(void)
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{
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return topology_amd_nodes_per_pkg() * topology_max_packages();
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}
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#ifdef CONFIG_AMD_NODE
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int __must_check amd_smn_read(u16 node, u32 address, u32 *value);
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int __must_check amd_smn_write(u16 node, u32 address, u32 value);
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/* Should only be used by the HSMP driver. */
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int __must_check amd_smn_hsmp_rdwr(u16 node, u32 address, u32 *value, bool write);
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#else
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static inline int __must_check amd_smn_read(u16 node, u32 address, u32 *value) { return -ENODEV; }
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static inline int __must_check amd_smn_write(u16 node, u32 address, u32 value) { return -ENODEV; }
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static inline int __must_check amd_smn_hsmp_rdwr(u16 node, u32 address, u32 *value, bool write)
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{
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return -ENODEV;
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}
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#endif /* CONFIG_AMD_NODE */
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/* helper for use with read_poll_timeout */
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static inline int smn_read_register(u32 reg)
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{
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int data, rc;
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rc = amd_smn_read(0, reg, &data);
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if (rc)
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return rc;
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return data;
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}
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#endif /*_ASM_X86_AMD_NODE_H_*/
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