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RISC-V uses xRET instructions on return from interrupt and to go back to user-space; the xRET instruction is not core serializing. Use FENCE.I for providing core serialization as follows: - by calling sync_core_before_usermode() on return from interrupt (cf. ipi_sync_core()), - via switch_mm() and sync_core_before_usermode() (respectively, for uthread->uthread and kthread->uthread transitions) before returning to user-space. On RISC-V, the serialization in switch_mm() is activated by resetting the icache_stale_mask of the mm at prepare_sync_core_cmd(). Suggested-by: Palmer Dabbelt <palmer@dabbelt.com> Signed-off-by: Andrea Parri <parri.andrea@gmail.com> Reviewed-by: Mathieu Desnoyers <mathieu.desnoyers@efficios.com> Link: https://lore.kernel.org/r/20240131144936.29190-5-parri.andrea@gmail.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
70 lines
2.3 KiB
Plaintext
70 lines
2.3 KiB
Plaintext
#
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# Feature name: membarrier-sync-core
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# Kconfig: ARCH_HAS_MEMBARRIER_SYNC_CORE
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# description: arch supports core serializing membarrier
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#
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# Architecture requirements
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#
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# * arm/arm64/powerpc/s390
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#
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# Rely on implicit context synchronization as a result of exception return
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# when returning from IPI handler, and when returning to user-space.
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#
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# * riscv
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#
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# riscv uses xRET as return from interrupt and to return to user-space.
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#
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# Given that xRET is not core serializing, we rely on FENCE.I for providing
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# core serialization:
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#
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# - by calling sync_core_before_usermode() on return from interrupt (cf.
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# ipi_sync_core()),
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#
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# - via switch_mm() and sync_core_before_usermode() (respectively, for
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# uthread->uthread and kthread->uthread transitions) before returning
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# to user-space.
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#
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# The serialization in switch_mm() is activated by prepare_sync_core_cmd().
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#
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# * x86
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#
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# x86-32 uses IRET as return from interrupt, which takes care of the IPI.
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# However, it uses both IRET and SYSEXIT to go back to user-space. The IRET
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# instruction is core serializing, but not SYSEXIT.
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#
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# x86-64 uses IRET as return from interrupt, which takes care of the IPI.
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# However, it can return to user-space through either SYSRETL (compat code),
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# SYSRETQ, or IRET.
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#
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# Given that neither SYSRET{L,Q}, nor SYSEXIT, are core serializing, we rely
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# instead on write_cr3() performed by switch_mm() to provide core serialization
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# after changing the current mm, and deal with the special case of kthread ->
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# uthread (temporarily keeping current mm into active_mm) by issuing a
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# sync_core_before_usermode() in that specific case.
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#
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-----------------------
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| arch |status|
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-----------------------
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| alpha: | TODO |
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| arc: | TODO |
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| arm: | ok |
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| arm64: | ok |
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| csky: | TODO |
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| hexagon: | TODO |
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| loongarch: | TODO |
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| m68k: | TODO |
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| microblaze: | TODO |
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| mips: | TODO |
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| nios2: | TODO |
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| openrisc: | TODO |
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| parisc: | TODO |
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| powerpc: | ok |
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| riscv: | ok |
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| s390: | ok |
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| sh: | TODO |
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| sparc: | TODO |
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| um: | TODO |
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| x86: | ok |
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| xtensa: | TODO |
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-----------------------
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