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4cb46c1c73
We're adding a new IWLMLD opmode for just BZ and later devices. If that's enabled but IWLMVM isn't, the build fails because 22000 family configs aren't built but BZ and later refer to it. Rather than trying to make some new file to build it in all cases, just copy the small struct. Signed-off-by: Johannes Berg <johannes.berg@intel.com> Reviewed-by: Emmanuel Grumbach <emmanuel.grumbach@intel.com> Signed-off-by: Miri Korenblit <miriam.rachel.korenblit@intel.com> Link: https://patch.msgid.link/20250205145347.1d6186c23bee.I3c61a6c9e0db3ba6eea4dac63e1547945ad01703@changeid Signed-off-by: Johannes Berg <johannes.berg@intel.com>
184 lines
5.6 KiB
C
184 lines
5.6 KiB
C
// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
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/*
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* Copyright (C) 2015-2017 Intel Deutschland GmbH
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* Copyright (C) 2018-2024 Intel Corporation
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*/
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#include <linux/module.h>
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#include <linux/stringify.h>
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#include "iwl-config.h"
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#include "iwl-prph.h"
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#include "fw/api/txq.h"
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/* Highest firmware API version supported */
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#define IWL_BZ_UCODE_API_MAX 96
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/* Lowest firmware API version supported */
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#define IWL_BZ_UCODE_API_MIN 92
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/* NVM versions */
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#define IWL_BZ_NVM_VERSION 0x0a1d
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/* Memory offsets and lengths */
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#define IWL_BZ_DCCM_OFFSET 0x800000 /* LMAC1 */
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#define IWL_BZ_DCCM_LEN 0x10000 /* LMAC1 */
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#define IWL_BZ_DCCM2_OFFSET 0x880000
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#define IWL_BZ_DCCM2_LEN 0x8000
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#define IWL_BZ_SMEM_OFFSET 0x400000
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#define IWL_BZ_SMEM_LEN 0xD0000
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#define IWL_BZ_A_HR_B_FW_PRE "iwlwifi-bz-a0-hr-b0"
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#define IWL_BZ_A_GF_A_FW_PRE "iwlwifi-bz-a0-gf-a0"
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#define IWL_BZ_A_GF4_A_FW_PRE "iwlwifi-bz-a0-gf4-a0"
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#define IWL_BZ_A_FM_B_FW_PRE "iwlwifi-bz-a0-fm-b0"
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#define IWL_BZ_A_FM_C_FW_PRE "iwlwifi-bz-a0-fm-c0"
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#define IWL_BZ_A_FM4_B_FW_PRE "iwlwifi-bz-a0-fm4-b0"
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#define IWL_GL_B_FM_B_FW_PRE "iwlwifi-gl-b0-fm-b0"
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#define IWL_GL_C_FM_C_FW_PRE "iwlwifi-gl-c0-fm-c0"
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#define IWL_BZ_A_HR_B_MODULE_FIRMWARE(api) \
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IWL_BZ_A_HR_B_FW_PRE "-" __stringify(api) ".ucode"
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static const struct iwl_base_params iwl_bz_base_params = {
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.eeprom_size = OTP_LOW_IMAGE_SIZE_32K,
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.num_of_queues = 512,
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.max_tfd_queue_size = 65536,
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.shadow_ram_support = true,
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.led_compensation = 57,
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.wd_timeout = IWL_LONG_WD_TIMEOUT,
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.max_event_log_size = 512,
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.shadow_reg_enable = true,
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.pcie_l1_allowed = true,
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};
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const struct iwl_ht_params iwl_bz_ht_params = {
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.stbc = true,
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.ldpc = true,
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.ht40_bands = BIT(NL80211_BAND_2GHZ) | BIT(NL80211_BAND_5GHZ) |
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BIT(NL80211_BAND_6GHZ),
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};
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#define IWL_DEVICE_BZ_COMMON \
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.ucode_api_max = IWL_BZ_UCODE_API_MAX, \
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.ucode_api_min = IWL_BZ_UCODE_API_MIN, \
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.led_mode = IWL_LED_RF_STATE, \
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.nvm_hw_section_num = 10, \
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.non_shared_ant = ANT_B, \
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.dccm_offset = IWL_BZ_DCCM_OFFSET, \
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.dccm_len = IWL_BZ_DCCM_LEN, \
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.dccm2_offset = IWL_BZ_DCCM2_OFFSET, \
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.dccm2_len = IWL_BZ_DCCM2_LEN, \
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.smem_offset = IWL_BZ_SMEM_OFFSET, \
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.smem_len = IWL_BZ_SMEM_LEN, \
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.apmg_not_supported = true, \
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.trans.mq_rx_supported = true, \
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.vht_mu_mimo_supported = true, \
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.mac_addr_from_csr = 0x30, \
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.nvm_ver = IWL_BZ_NVM_VERSION, \
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.trans.rf_id = true, \
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.trans.gen2 = true, \
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.nvm_type = IWL_NVM_EXT, \
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.dbgc_supported = true, \
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.min_umac_error_event_table = 0xD0000, \
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.d3_debug_data_base_addr = 0x401000, \
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.d3_debug_data_length = 60 * 1024, \
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.mon_smem_regs = { \
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.write_ptr = { \
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.addr = LDBG_M2S_BUF_WPTR, \
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.mask = LDBG_M2S_BUF_WPTR_VAL_MSK, \
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}, \
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.cycle_cnt = { \
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.addr = LDBG_M2S_BUF_WRAP_CNT, \
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.mask = LDBG_M2S_BUF_WRAP_CNT_VAL_MSK, \
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}, \
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}, \
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.trans.umac_prph_offset = 0x300000, \
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.trans.device_family = IWL_DEVICE_FAMILY_BZ, \
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.trans.base_params = &iwl_bz_base_params, \
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.min_txq_size = 128, \
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.gp2_reg_addr = 0xd02c68, \
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.min_ba_txq_size = IWL_DEFAULT_QUEUE_SIZE_EHT, \
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.mon_dram_regs = { \
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.write_ptr = { \
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.addr = DBGC_CUR_DBGBUF_STATUS, \
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.mask = DBGC_CUR_DBGBUF_STATUS_OFFSET_MSK, \
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}, \
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.cycle_cnt = { \
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.addr = DBGC_DBGBUF_WRAP_AROUND, \
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.mask = 0xffffffff, \
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}, \
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.cur_frag = { \
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.addr = DBGC_CUR_DBGBUF_STATUS, \
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.mask = DBGC_CUR_DBGBUF_STATUS_IDX_MSK, \
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}, \
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}, \
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.mon_dbgi_regs = { \
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.write_ptr = { \
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.addr = DBGI_SRAM_FIFO_POINTERS, \
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.mask = DBGI_SRAM_FIFO_POINTERS_WR_PTR_MSK, \
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}, \
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}
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#define IWL_DEVICE_BZ \
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IWL_DEVICE_BZ_COMMON, \
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.ht_params = &iwl_bz_ht_params
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/*
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* This size was picked according to 8 MSDUs inside 512 A-MSDUs in an
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* A-MPDU, with additional overhead to account for processing time.
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*/
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#define IWL_NUM_RBDS_BZ_EHT (512 * 16)
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const struct iwl_cfg_trans_params iwl_bz_trans_cfg = {
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.device_family = IWL_DEVICE_FAMILY_BZ,
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.base_params = &iwl_bz_base_params,
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.mq_rx_supported = true,
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.rf_id = true,
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.gen2 = true,
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.integrated = true,
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.umac_prph_offset = 0x300000,
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.xtal_latency = 12000,
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.low_latency_xtal = true,
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.ltr_delay = IWL_CFG_TRANS_LTR_DELAY_2500US,
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};
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const struct iwl_cfg_trans_params iwl_gl_trans_cfg = {
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.device_family = IWL_DEVICE_FAMILY_BZ,
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.base_params = &iwl_bz_base_params,
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.mq_rx_supported = true,
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.rf_id = true,
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.gen2 = true,
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.umac_prph_offset = 0x300000,
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.xtal_latency = 12000,
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.low_latency_xtal = true,
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};
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const char iwl_fm_name[] = "Intel(R) Wi-Fi 7 BE201 320MHz";
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const char iwl_wh_name[] = "Intel(R) Wi-Fi 7 BE211 320MHz";
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const char iwl_gl_name[] = "Intel(R) Wi-Fi 7 BE200 320MHz";
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const char iwl_mtp_name[] = "Intel(R) Wi-Fi 7 BE202 160MHz";
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const struct iwl_cfg iwl_cfg_bz = {
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.fw_name_mac = "bz",
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.uhb_supported = true,
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IWL_DEVICE_BZ,
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.features = IWL_TX_CSUM_NETIF_FLAGS | NETIF_F_RXCSUM,
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.num_rbds = IWL_NUM_RBDS_BZ_EHT,
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};
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const struct iwl_cfg iwl_cfg_gl = {
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.fw_name_mac = "gl",
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.uhb_supported = true,
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IWL_DEVICE_BZ,
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.features = IWL_TX_CSUM_NETIF_FLAGS | NETIF_F_RXCSUM,
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.num_rbds = IWL_NUM_RBDS_BZ_EHT,
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};
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MODULE_FIRMWARE(IWL_BZ_A_HR_B_MODULE_FIRMWARE(IWL_BZ_UCODE_API_MAX));
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IWL_FW_AND_PNVM(IWL_BZ_A_GF_A_FW_PRE, IWL_BZ_UCODE_API_MAX);
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IWL_FW_AND_PNVM(IWL_BZ_A_GF4_A_FW_PRE, IWL_BZ_UCODE_API_MAX);
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IWL_FW_AND_PNVM(IWL_BZ_A_FM_B_FW_PRE, IWL_BZ_UCODE_API_MAX);
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IWL_FW_AND_PNVM(IWL_BZ_A_FM_C_FW_PRE, IWL_BZ_UCODE_API_MAX);
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IWL_FW_AND_PNVM(IWL_BZ_A_FM4_B_FW_PRE, IWL_BZ_UCODE_API_MAX);
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IWL_FW_AND_PNVM(IWL_GL_B_FM_B_FW_PRE, IWL_BZ_UCODE_API_MAX);
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IWL_FW_AND_PNVM(IWL_GL_C_FM_C_FW_PRE, IWL_BZ_UCODE_API_MAX);
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