Heiko Stuebner d20ec75292 riscv: implement cache-management errata for T-Head SoCs ...

The T-Head C906 and C910 implement a scheme for handling
cache operations different from the generic Zicbom extension.

Add an errata for it next to the generic dma coherency ops.

Reviewed-by: Samuel Holland <samuel@sholland.org>
Tested-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Guo Ren <guoren@kernel.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Link: https://lore.kernel.org/r/20220706231536.2041855-5-heiko@sntech.de
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>

2022-08-03 17:29:59 -07:00

..

errata.c

riscv: implement cache-management errata for T-Head SoCs

2022-08-03 17:29:59 -07:00

Makefile

riscv: add memory-type errata for T-Head

2022-05-11 21:36:33 -07:00