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Kazuya Mizuguchi 29c7f3e68e usb: renesas_usbhs: Fix DMAC sequence for receiving zero-length packet

The DREQE bit of the DnFIFOSEL should be set to 1 after the DE bit of
USB-DMAC on R-Car SoCs is set to 1 after the USB-DMAC received a
zero-length packet. Otherwise, a transfer completion interruption
of USB-DMAC doesn't happen. Even if the driver changes the sequence,
normal operations (transmit/receive without zero-length packet) will
not cause any side-effects. So, this patch fixes the sequence anyway.

Signed-off-by: Kazuya Mizuguchi <kazuya.mizuguchi.ks@renesas.com>
[shimoda: revise the commit log]
Fixes: e73a9891b3 ("usb: renesas_usbhs: add DMAEngine support")
Cc: <stable@vger.kernel.org> # v3.1+
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>

2017-10-11 13:13:52 +03:00

common.c

usb: renesas_usbhs: fix usbhsc_resume() for !USBHSF_RUNTIME_PWCTRL

2017-07-19 10:38:16 +03:00

common.h

usb: renesas_usbhs: add support for USB-DMAC

2015-03-13 10:41:19 -05:00

fifo.c

usb: renesas_usbhs: Fix DMAC sequence for receiving zero-length packet

2017-10-11 13:13:52 +03:00

fifo.h

usb: renesas_usbhs: constify usbhs_pkt_handle structures