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linux/drivers/gpu/drm/amd/include/asic_reg/gc
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Alex Deucher 5d5b71e8a0 drm/amdgpu: add the GC 10.3 VRS registers 
Add the VRS registers.

Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-09-17 23:05:42 -04:00
..
gc_9_0_default.h
drm/amdgpu: remove some old gc 9.x registers
2017-12-13 17:28:08 -05:00
gc_9_0_offset.h
drm/amd/amdgpu: Fix SQ_DEBUG_STS_GLOBAL* registers
2020-07-01 01:59:21 -04:00
gc_9_0_sh_mask.h
drm/amd/amdgpu: Add SQ_DEBUG_STS_GLOBAL* registers/bits
2020-07-01 01:59:19 -04:00
gc_9_1_offset.h
drm/amd/amdgpu: Fix SQ_DEBUG_STS_GLOBAL* registers
2020-07-01 01:59:21 -04:00
gc_9_1_sh_mask.h
drm/amd/amdgpu: Add SQ_DEBUG_STS_GLOBAL* registers/bits
2020-07-01 01:59:19 -04:00
gc_9_2_1_offset.h
drm/amd/amdgpu: Fix SQ_DEBUG_STS_GLOBAL* registers
2020-07-01 01:59:21 -04:00
gc_9_2_1_sh_mask.h
drm/amd/amdgpu: Add SQ_DEBUG_STS_GLOBAL* registers/bits
2020-07-01 01:59:19 -04:00
gc_9_4_1_offset.h
drm/amdgpu: add EDC counter registers of gc for Arcturus
2020-01-22 16:36:22 -05:00
gc_9_4_1_sh_mask.h
drm/amdgpu: add EDC counter registers of gc for Arcturus
2020-01-22 16:36:22 -05:00
gc_10_1_0_default.h
drm/amdgpu: add GC 10.1 register headers (v4)
2019-06-20 15:54:35 -05:00
gc_10_1_0_offset.h
drm/amd/amdgpu: Fix offset for SQ_DEBUG_STS_GLOBAL on gfx10 (v2)
2020-07-01 01:59:22 -04:00
gc_10_1_0_sh_mask.h
drm/amd/amdgpu: Add SQ_DEBUG_STS_GLOBAL* registers/bits
2020-07-01 01:59:19 -04:00
gc_10_3_0_default.h
drm/amdgpu: add the GC 10.3 VRS registers
2020-09-17 23:05:42 -04:00
gc_10_3_0_offset.h
drm/amdgpu: add the GC 10.3 VRS registers
2020-09-17 23:05:42 -04:00
gc_10_3_0_sh_mask.h
drm/amdgpu: add the GC 10.3 VRS registers
2020-09-17 23:05:42 -04:00