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c8081b2a8a
While updating the source OUI on the sink the driver should avoid
writing the OUI if it's already up-to-date to prevent the sink from
resetting itself in response to the update. On eDP - the only output
type where the OUI was updated so far - the driver ensured this by
comparing the current source OUI DPCD register values with the expected
Intel OUI value, skipping the update in case of a match. On some non-eDP
sinks - at least on Synaptics branch devices - this method doesn't work,
since the source OUI DPCD registers read back as all 0, even after
updating the registers.
Handle the above kind of sinks by tracking when the OUI was updated and
so should be valid, regardless of what the DPCD registers contain.
eDP sinks reset the written source OUI value when the panel power is
disabled, invalidate the OUI state accordingly.
This is required by a follow-up patch updating the source OUI for
non-eDP sink types as well.
v2: Fix setting intel_dp::oui_valid=true, if the DPCD register contains
already the expected value.
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20241025160259.3088727-5-imre.deak@intel.com
211 lines
9.0 KiB
C
211 lines
9.0 KiB
C
/* SPDX-License-Identifier: MIT */
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/*
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* Copyright © 2019 Intel Corporation
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*/
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#ifndef __INTEL_DP_H__
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#define __INTEL_DP_H__
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#include <linux/types.h>
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enum intel_output_format;
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enum pipe;
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enum port;
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struct drm_connector_state;
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struct drm_encoder;
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struct drm_i915_private;
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struct drm_modeset_acquire_ctx;
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struct drm_dp_vsc_sdp;
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struct intel_atomic_state;
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struct intel_connector;
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struct intel_crtc_state;
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struct intel_digital_port;
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struct intel_dp;
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struct intel_encoder;
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struct link_config_limits {
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int min_rate, max_rate;
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int min_lane_count, max_lane_count;
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struct {
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/* Uncompressed DSC input or link output bpp in 1 bpp units */
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int min_bpp, max_bpp;
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} pipe;
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struct {
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/* Compressed or uncompressed link output bpp in 1/16 bpp units */
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int min_bpp_x16, max_bpp_x16;
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} link;
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};
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void intel_edp_fixup_vbt_bpp(struct intel_encoder *encoder, int pipe_bpp);
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bool intel_dp_limited_color_range(const struct intel_crtc_state *crtc_state,
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const struct drm_connector_state *conn_state);
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int intel_dp_min_bpp(enum intel_output_format output_format);
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void intel_dp_init_modeset_retry_work(struct intel_connector *connector);
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void
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intel_dp_queue_modeset_retry_for_link(struct intel_atomic_state *state,
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struct intel_encoder *encoder,
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const struct intel_crtc_state *crtc_state);
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bool intel_dp_init_connector(struct intel_digital_port *dig_port,
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struct intel_connector *intel_connector);
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void intel_dp_connector_sync_state(struct intel_connector *connector,
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const struct intel_crtc_state *crtc_state);
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void intel_dp_set_link_params(struct intel_dp *intel_dp,
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int link_rate, int lane_count);
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int intel_dp_get_active_pipes(struct intel_dp *intel_dp,
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struct drm_modeset_acquire_ctx *ctx,
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u8 *pipe_mask);
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void intel_dp_flush_connector_commits(struct intel_connector *connector);
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void intel_dp_link_check(struct intel_encoder *encoder);
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void intel_dp_check_link_state(struct intel_dp *intel_dp);
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void intel_dp_set_power(struct intel_dp *intel_dp, u8 mode);
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void intel_dp_configure_protocol_converter(struct intel_dp *intel_dp,
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const struct intel_crtc_state *crtc_state);
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void intel_dp_sink_enable_decompression(struct intel_atomic_state *state,
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struct intel_connector *connector,
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const struct intel_crtc_state *new_crtc_state);
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void intel_dp_sink_disable_decompression(struct intel_atomic_state *state,
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struct intel_connector *connector,
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const struct intel_crtc_state *old_crtc_state);
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void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder);
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void intel_dp_encoder_shutdown(struct intel_encoder *intel_encoder);
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void intel_dp_encoder_flush_work(struct drm_encoder *encoder);
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int intel_dp_compute_config(struct intel_encoder *encoder,
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struct intel_crtc_state *pipe_config,
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struct drm_connector_state *conn_state);
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int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
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struct intel_crtc_state *pipe_config,
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struct drm_connector_state *conn_state,
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struct link_config_limits *limits,
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int timeslots,
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bool recompute_pipe_bpp);
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void intel_dp_audio_compute_config(struct intel_encoder *encoder,
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struct intel_crtc_state *pipe_config,
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struct drm_connector_state *conn_state);
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bool intel_dp_has_hdmi_sink(struct intel_dp *intel_dp);
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bool intel_dp_is_edp(struct intel_dp *intel_dp);
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bool intel_dp_is_uhbr(const struct intel_crtc_state *crtc_state);
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bool intel_dp_has_dsc(const struct intel_connector *connector);
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int intel_dp_link_symbol_size(int rate);
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int intel_dp_link_symbol_clock(int rate);
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bool intel_dp_is_port_edp(struct drm_i915_private *dev_priv, enum port port);
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enum irqreturn intel_dp_hpd_pulse(struct intel_digital_port *dig_port,
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bool long_hpd);
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void intel_edp_backlight_on(const struct intel_crtc_state *crtc_state,
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const struct drm_connector_state *conn_state);
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void intel_edp_backlight_off(const struct drm_connector_state *conn_state);
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void intel_edp_fixup_vbt_bpp(struct intel_encoder *encoder, int pipe_bpp);
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void intel_dp_mst_suspend(struct drm_i915_private *dev_priv);
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void intel_dp_mst_resume(struct drm_i915_private *dev_priv);
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int intel_dp_max_source_lane_count(struct intel_digital_port *dig_port);
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int intel_dp_max_link_rate(struct intel_dp *intel_dp);
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int intel_dp_max_lane_count(struct intel_dp *intel_dp);
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int intel_dp_config_required_rate(const struct intel_crtc_state *crtc_state);
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int intel_dp_rate_select(struct intel_dp *intel_dp, int rate);
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int intel_dp_max_common_rate(struct intel_dp *intel_dp);
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int intel_dp_max_common_lane_count(struct intel_dp *intel_dp);
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int intel_dp_common_rate(struct intel_dp *intel_dp, int index);
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int intel_dp_rate_index(const int *rates, int len, int rate);
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int intel_dp_link_config_index(struct intel_dp *intel_dp, int link_rate, int lane_count);
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void intel_dp_link_config_get(struct intel_dp *intel_dp, int idx, int *link_rate, int *lane_count);
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void intel_dp_update_sink_caps(struct intel_dp *intel_dp);
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void intel_dp_reset_link_params(struct intel_dp *intel_dp);
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void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
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u8 *link_bw, u8 *rate_select);
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bool intel_dp_source_supports_tps3(struct drm_i915_private *i915);
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bool intel_dp_source_supports_tps4(struct drm_i915_private *i915);
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int intel_dp_link_required(int pixel_clock, int bpp);
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int intel_dp_effective_data_rate(int pixel_clock, int bpp_x16,
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int bw_overhead);
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int intel_dp_max_link_data_rate(struct intel_dp *intel_dp,
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int max_dprx_rate, int max_dprx_lanes);
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bool intel_dp_joiner_needs_dsc(struct drm_i915_private *i915,
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int num_joined_pipes);
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bool intel_dp_has_joiner(struct intel_dp *intel_dp);
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bool intel_dp_needs_vsc_sdp(const struct intel_crtc_state *crtc_state,
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const struct drm_connector_state *conn_state);
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void intel_dp_set_infoframes(struct intel_encoder *encoder, bool enable,
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const struct intel_crtc_state *crtc_state,
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const struct drm_connector_state *conn_state);
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void intel_read_dp_sdp(struct intel_encoder *encoder,
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struct intel_crtc_state *crtc_state,
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unsigned int type);
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void intel_digital_port_lock(struct intel_encoder *encoder);
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void intel_digital_port_unlock(struct intel_encoder *encoder);
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bool intel_digital_port_connected(struct intel_encoder *encoder);
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bool intel_digital_port_connected_locked(struct intel_encoder *encoder);
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int intel_dp_dsc_compute_max_bpp(const struct intel_connector *connector,
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u8 dsc_max_bpc);
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u16 intel_dp_dsc_get_max_compressed_bpp(struct drm_i915_private *i915,
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u32 link_clock, u32 lane_count,
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u32 mode_clock, u32 mode_hdisplay,
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int num_joined_pipes,
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enum intel_output_format output_format,
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u32 pipe_bpp,
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u32 timeslots);
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int intel_dp_dsc_sink_min_compressed_bpp(struct intel_crtc_state *pipe_config);
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int intel_dp_dsc_sink_max_compressed_bpp(const struct intel_connector *connector,
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struct intel_crtc_state *pipe_config,
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int bpc);
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u8 intel_dp_dsc_get_slice_count(const struct intel_connector *connector,
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int mode_clock, int mode_hdisplay,
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int num_joined_pipes);
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int intel_dp_num_joined_pipes(struct intel_dp *intel_dp,
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struct intel_connector *connector,
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int hdisplay, int clock);
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static inline unsigned int intel_dp_unused_lane_mask(int lane_count)
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{
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return ~((1 << lane_count) - 1) & 0xf;
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}
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bool intel_dp_supports_fec(struct intel_dp *intel_dp,
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const struct intel_connector *connector,
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const struct intel_crtc_state *pipe_config);
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u32 intel_dp_mode_to_fec_clock(u32 mode_clock);
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int intel_dp_bw_fec_overhead(bool fec_enabled);
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bool intel_dp_supports_fec(struct intel_dp *intel_dp,
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const struct intel_connector *connector,
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const struct intel_crtc_state *pipe_config);
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bool intel_dp_supports_dsc(const struct intel_connector *connector,
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const struct intel_crtc_state *crtc_state);
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u32 intel_dp_dsc_nearest_valid_bpp(struct drm_i915_private *i915, u32 bpp, u32 pipe_bpp);
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void intel_ddi_update_pipe(struct intel_atomic_state *state,
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struct intel_encoder *encoder,
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const struct intel_crtc_state *crtc_state,
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const struct drm_connector_state *conn_state);
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bool intel_dp_initial_fastset_check(struct intel_encoder *encoder,
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struct intel_crtc_state *crtc_state);
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void intel_dp_sync_state(struct intel_encoder *encoder,
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const struct intel_crtc_state *crtc_state);
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void intel_dp_check_frl_training(struct intel_dp *intel_dp);
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void intel_dp_pcon_dsc_configure(struct intel_dp *intel_dp,
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const struct intel_crtc_state *crtc_state);
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void intel_dp_invalidate_source_oui(struct intel_dp *intel_dp);
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void intel_dp_wait_source_oui(struct intel_dp *intel_dp);
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int intel_dp_output_bpp(enum intel_output_format output_format, int bpp);
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bool
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intel_dp_compute_config_link_bpp_limits(struct intel_dp *intel_dp,
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const struct intel_crtc_state *crtc_state,
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bool dsc,
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struct link_config_limits *limits);
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void intel_dp_get_dsc_sink_cap(u8 dpcd_rev, struct intel_connector *connector);
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bool intel_dp_has_gamut_metadata_dip(struct intel_encoder *encoder);
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bool intel_dp_link_params_valid(struct intel_dp *intel_dp, int link_rate,
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u8 lane_count);
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bool intel_dp_has_connector(struct intel_dp *intel_dp,
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const struct drm_connector_state *conn_state);
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#endif /* __INTEL_DP_H__ */
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