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ae03d70748
There are some minor changes to pmdemand handling on Xe3: - Active scalers are no longer tracked. We can simply skip the readout and programming of this field. - Active dbuf slices are no longer tracked. We should skip the readout and programming of this field and also make sure that it stays 0 in our software bookkeeping so that we won't erroneously return true from intel_pmdemand_needs_update() due to mismatches. - Even though there aren't enough pipes to utilize them, the size of the 'active pipes' field has expanded to four bits, taking over the register bits previously used for dbuf slices. Since the lower bits of the mask have moved, we need to update our reads/writes to handle this properly. v2: active pipes is no longer always max 3, add in the ability to go to 4 for PTL. v3: use intel_display for display_ver check, use INTEL_NUM_PIPES v4: add a conditional for number of pipes macro vs using 3. v5: reverse conditional order of v4. v6: undo v5 and fix num_pipes assignment v7: pass display struct instead of i915, checkpatch fix v8: Alignment issue Bspec: 68883, 69125 Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: Matt Atwood <matthew.s.atwood@intel.com> Signed-off-by: Clint Taylor <Clinton.A.Taylor@intel.com> Reviewed-by: Vinod Govindapillai <vinod.govindapillai@intel.com> Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20241028193015.3241858-2-clinton.a.taylor@intel.com
67 lines
2.0 KiB
C
67 lines
2.0 KiB
C
/* SPDX-License-Identifier: MIT */
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/*
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* Copyright © 2023 Intel Corporation
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*/
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#ifndef __INTEL_PMDEMAND_H__
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#define __INTEL_PMDEMAND_H__
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#include "intel_display_limits.h"
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#include "intel_global_state.h"
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struct drm_i915_private;
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struct intel_atomic_state;
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struct intel_crtc_state;
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struct intel_encoder;
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struct intel_plane_state;
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struct pmdemand_params {
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u16 qclk_gv_bw;
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u8 voltage_index;
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u8 qclk_gv_index;
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u8 active_pipes;
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u8 active_dbufs; /* pre-Xe3 only */
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/* Total number of non type C active phys from active_phys_mask */
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u8 active_phys;
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u8 plls;
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u16 cdclk_freq_mhz;
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/* max from ddi_clocks[] */
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u16 ddiclk_max;
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u8 scalers; /* pre-Xe3 only */
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};
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struct intel_pmdemand_state {
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struct intel_global_state base;
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/* Maintain a persistent list of port clocks across all crtcs */
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int ddi_clocks[I915_MAX_PIPES];
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/* Maintain a persistent list of non type C phys mask */
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u16 active_combo_phys_mask;
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/* Parameters to be configured in the pmdemand registers */
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struct pmdemand_params params;
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};
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#define to_intel_pmdemand_state(global_state) \
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container_of_const((global_state), struct intel_pmdemand_state, base)
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void intel_pmdemand_init_early(struct drm_i915_private *i915);
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int intel_pmdemand_init(struct drm_i915_private *i915);
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void intel_pmdemand_init_pmdemand_params(struct drm_i915_private *i915,
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struct intel_pmdemand_state *pmdemand_state);
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void intel_pmdemand_update_port_clock(struct drm_i915_private *i915,
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struct intel_pmdemand_state *pmdemand_state,
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enum pipe pipe, int port_clock);
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void intel_pmdemand_update_phys_mask(struct drm_i915_private *i915,
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struct intel_encoder *encoder,
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struct intel_pmdemand_state *pmdemand_state,
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bool clear_bit);
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void intel_pmdemand_program_dbuf(struct drm_i915_private *i915,
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u8 dbuf_slices);
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void intel_pmdemand_pre_plane_update(struct intel_atomic_state *state);
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void intel_pmdemand_post_plane_update(struct intel_atomic_state *state);
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int intel_pmdemand_atomic_check(struct intel_atomic_state *state);
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#endif /* __INTEL_PMDEMAND_H__ */
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