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61e79860b4
commit 6892517629 upstream.
When invalidating guest TLBs, special care must be taken to
actually shoot the guest TLBs and not the host ones if we're
running on a VHE system. This is controlled by the HCR_EL2.TGE
bit, which we forget to clear before invalidating TLBs.
Address the issue by introducing two wrappers (__tlb_switch_to_guest
and __tlb_switch_to_host) that take care of both the VTTBR_EL2
and HCR_EL2.TGE switching.
Reported-by: Tomasz Nowicki <tnowicki@caviumnetworks.com>
Tested-by: Tomasz Nowicki <tnowicki@caviumnetworks.com>
Reviewed-by: Christoffer Dall <cdall@linaro.org>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
135 lines
3.3 KiB
C
135 lines
3.3 KiB
C
/*
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* Copyright (C) 2015 - ARM Ltd
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* Author: Marc Zyngier <marc.zyngier@arm.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <asm/kvm_hyp.h>
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static void __hyp_text __tlb_switch_to_guest_vhe(struct kvm *kvm)
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{
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u64 val;
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/*
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* With VHE enabled, we have HCR_EL2.{E2H,TGE} = {1,1}, and
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* most TLB operations target EL2/EL0. In order to affect the
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* guest TLBs (EL1/EL0), we need to change one of these two
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* bits. Changing E2H is impossible (goodbye TTBR1_EL2), so
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* let's flip TGE before executing the TLB operation.
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*/
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write_sysreg(kvm->arch.vttbr, vttbr_el2);
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val = read_sysreg(hcr_el2);
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val &= ~HCR_TGE;
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write_sysreg(val, hcr_el2);
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isb();
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}
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static void __hyp_text __tlb_switch_to_guest_nvhe(struct kvm *kvm)
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{
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write_sysreg(kvm->arch.vttbr, vttbr_el2);
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isb();
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}
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static hyp_alternate_select(__tlb_switch_to_guest,
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__tlb_switch_to_guest_nvhe,
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__tlb_switch_to_guest_vhe,
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ARM64_HAS_VIRT_HOST_EXTN);
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static void __hyp_text __tlb_switch_to_host_vhe(struct kvm *kvm)
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{
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/*
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* We're done with the TLB operation, let's restore the host's
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* view of HCR_EL2.
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*/
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write_sysreg(0, vttbr_el2);
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write_sysreg(HCR_HOST_VHE_FLAGS, hcr_el2);
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}
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static void __hyp_text __tlb_switch_to_host_nvhe(struct kvm *kvm)
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{
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write_sysreg(0, vttbr_el2);
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}
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static hyp_alternate_select(__tlb_switch_to_host,
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__tlb_switch_to_host_nvhe,
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__tlb_switch_to_host_vhe,
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ARM64_HAS_VIRT_HOST_EXTN);
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void __hyp_text __kvm_tlb_flush_vmid_ipa(struct kvm *kvm, phys_addr_t ipa)
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{
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dsb(ishst);
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/* Switch to requested VMID */
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kvm = kern_hyp_va(kvm);
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__tlb_switch_to_guest()(kvm);
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/*
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* We could do so much better if we had the VA as well.
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* Instead, we invalidate Stage-2 for this IPA, and the
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* whole of Stage-1. Weep...
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*/
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ipa >>= 12;
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asm volatile("tlbi ipas2e1is, %0" : : "r" (ipa));
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/*
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* We have to ensure completion of the invalidation at Stage-2,
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* since a table walk on another CPU could refill a TLB with a
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* complete (S1 + S2) walk based on the old Stage-2 mapping if
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* the Stage-1 invalidation happened first.
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*/
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dsb(ish);
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asm volatile("tlbi vmalle1is" : : );
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dsb(ish);
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isb();
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__tlb_switch_to_host()(kvm);
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}
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void __hyp_text __kvm_tlb_flush_vmid(struct kvm *kvm)
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{
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dsb(ishst);
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/* Switch to requested VMID */
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kvm = kern_hyp_va(kvm);
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__tlb_switch_to_guest()(kvm);
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asm volatile("tlbi vmalls12e1is" : : );
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dsb(ish);
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isb();
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__tlb_switch_to_host()(kvm);
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}
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void __hyp_text __kvm_tlb_flush_local_vmid(struct kvm_vcpu *vcpu)
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{
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struct kvm *kvm = kern_hyp_va(kern_hyp_va(vcpu)->kvm);
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/* Switch to requested VMID */
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__tlb_switch_to_guest()(kvm);
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asm volatile("tlbi vmalle1" : : );
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dsb(nsh);
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isb();
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__tlb_switch_to_host()(kvm);
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}
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void __hyp_text __kvm_flush_vm_context(void)
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{
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dsb(ishst);
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asm volatile("tlbi alle1is \n"
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"ic ialluis ": : );
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dsb(ish);
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}
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