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Signed-off-by: popcornmix <popcornmix@gmail.com> usb: dwc: fix lockdep false positive Signed-off-by: Kari Suvanto <karis79@gmail.com> usb: dwc: fix inconsistent lock state Signed-off-by: Kari Suvanto <karis79@gmail.com> Add FIQ patch to dwc_otg driver. Enable with dwc_otg.fiq_fix_enable=1. Should give about 10% more ARM performance. Thanks to Gordon and Costas Avoid dynamic memory allocation for channel lock in USB driver. Thanks ddv2005. Add NAK holdoff scheme. Enabled by default, disable with dwc_otg.nak_holdoff_enable=0. Thanks gsh Make sure we wait for the reset to finish dwc_otg: fix bug in dwc_otg_hcd.c resulting in silent kernel memory corruption, escalating to OOPS under high USB load. dwc_otg: Fix unsafe access of QTD during URB enqueue In dwc_otg_hcd_urb_enqueue during qtd creation, it was possible that the transaction could complete almost immediately after the qtd was assigned to a host channel during URB enqueue, which meant the qtd pointer was no longer valid having been completed and removed. Usually, this resulted in an OOPS during URB submission. By predetermining whether transactions need to be queued or not, this unsafe pointer access is avoided. This bug was only evident on the Pi model A where a device was attached that had no periodic endpoints (e.g. USB pendrive or some wlan devices). dwc_otg: Fix incorrect URB allocation error handling If the memory allocation for a dwc_otg_urb failed, the kernel would OOPS because for some reason a member of the *unallocated* struct was set to zero. Error handling changed to fail correctly. dwc_otg: fix potential use-after-free case in interrupt handler If a transaction had previously aborted, certain interrupts are enabled to track error counts and reset where necessary. On IN endpoints the host generates an ACK interrupt near-simultaneously with completion of transfer. In the case where this transfer had previously had an error, this results in a use-after-free on the QTD memory space with a 1-byte length being overwritten to 0x00. dwc_otg: add handling of SPLIT transaction data toggle errors Previously a data toggle error on packets from a USB1.1 device behind a TT would result in the Pi locking up as the driver never handled the associated interrupt. Patch adds basic retry mechanism and interrupt acknowledgement to cater for either a chance toggle error or for devices that have a broken initial toggle state (FT8U232/FT232BM). dwc_otg: implement tasklet for returning URBs to usbcore hcd layer The dwc_otg driver interrupt handler for transfer completion will spend a very long time with interrupts disabled when a URB is completed - this is because usb_hcd_giveback_urb is called from within the handler which for a USB device driver with complicated processing (e.g. webcam) will take an exorbitant amount of time to complete. This results in missed completion interrupts for other USB packets which lead to them being dropped due to microframe overruns. This patch splits returning the URB to the usb hcd layer into a high-priority tasklet. This will have most benefit for isochronous IN transfers but will also have incidental benefit where multiple periodic devices are active at once. dwc_otg: fix NAK holdoff and allow on split transactions only This corrects a bug where if a single active non-periodic endpoint had at least one transaction in its qh, on frnum == MAX_FRNUM the qh would get skipped and never get queued again. This would result in a silent device until error detection (automatic or otherwise) would either reset the device or flush and requeue the URBs. Additionally the NAK holdoff was enabled for all transactions - this would potentially stall a HS endpoint for 1ms if a previous error state enabled this interrupt and the next response was a NAK. Fix so that only split transactions get held off. dwc_otg: Call usb_hcd_unlink_urb_from_ep with lock held in completion handler usb_hcd_unlink_urb_from_ep must be called with the HCD lock held. Calling it asynchronously in the tasklet was not safe (regression inc4564d4a1a). This change unlinks it from the endpoint prior to queueing it for handling in the tasklet, and also adds a check to ensure the urb is OK to be unlinked before doing so. NULL pointer dereference kernel oopses had been observed in usb_hcd_giveback_urb when a USB device was unplugged/replugged during data transfer. This effect was reproduced using automated USB port power control, hundreds of replug events were performed during active transfers to confirm that the problem was eliminated. USB fix using a FIQ to implement split transactions This commit adds a FIQ implementaion that schedules the split transactions using a FIQ so we don't get held off by the interrupt latency of Linux dwc_otg: fix device attributes and avoid kernel warnings on boot dcw_otg: avoid logging function that can cause panics See: https://github.com/raspberrypi/firmware/issues/21 Thanks to cleverca22 for fix dwc_otg: mask correct interrupts after transaction error recovery The dwc_otg driver will unmask certain interrupts on a transaction that previously halted in the error state in order to reset the QTD error count. The various fine-grained interrupt handlers do not consider that other interrupts besides themselves were unmasked. By disabling the two other interrupts only ever enabled in DMA mode for this purpose, we can avoid unnecessary function calls in the IRQ handler. This will also prevent an unneccesary FIQ interrupt from being generated if the FIQ is enabled. dwc_otg: fiq: prevent FIQ thrash and incorrect state passing to IRQ In the case of a transaction to a device that had previously aborted due to an error, several interrupts are enabled to reset the error count when a device responds. This has the side-effect of making the FIQ thrash because the hardware will generate multiple instances of a NAK on an IN bulk/interrupt endpoint and multiple instances of ACK on an OUT bulk/interrupt endpoint. Make the FIQ mask and clear the associated interrupts. Additionally, on non-split transactions make sure that only unmasked interrupts are cleared. This caused a hard-to-trigger but serious race condition when you had the combination of an endpoint awaiting error recovery and a transaction completed on an endpoint - due to the sequencing and timing of interrupts generated by the dwc_otg core, it was possible to confuse the IRQ handler. Fix function tracing dwc_otg: whitespace cleanup in dwc_otg_urb_enqueue dwc_otg: prevent OOPSes during device disconnects The dwc_otg_urb_enqueue function is thread-unsafe. In particular the access of urb->hcpriv, usb_hcd_link_urb_to_ep, dwc_otg_urb->qtd and friends does not occur within a critical section and so if a device was unplugged during activity there was a high chance that the usbcore hub_thread would try to disable the endpoint with partially- formed entries in the URB queue. This would result in BUG() or null pointer dereferences. Fix so that access of urb->hcpriv, enqueuing to the hardware and adding to usbcore endpoint URB lists is contained within a single critical section. dwc_otg: prevent BUG() in TT allocation if hub address is > 16 A fixed-size array is used to track TT allocation. This was previously set to 16 which caused a crash because dwc_otg_hcd_allocate_port would read past the end of the array. This was hit if a hub was plugged in which enumerated as addr > 16, due to previous device resets or unplugs. Also add #ifdef FIQ_DEBUG around hcd->hub_port_alloc[], which grows to a large size if 128 hub addresses are supported. This field is for debug only for tracking which frame an allocate happened in. dwc_otg: make channel halts with unknown state less damaging If the IRQ received a channel halt interrupt through the FIQ with no other bits set, the IRQ would not release the host channel and never complete the URB. Add catchall handling to treat as a transaction error and retry. dwc_otg: fiq_split: use TTs with more granularity This fixes certain issues with split transaction scheduling. - Isochronous multi-packet OUT transactions now hog the TT until they are completed - this prevents hubs aborting transactions if they get a periodic start-split out-of-order - Don't perform TT allocation on non-periodic endpoints - this allows simultaneous use of the TT's bulk/control and periodic transaction buffers This commit will mainly affect USB audio playback. dwc_otg: fix potential sleep while atomic during urb enqueue Fixes a regression introduced witheb1b482a. Kmalloc called from dwc_otg_hcd_qtd_add / dwc_otg_hcd_qtd_create did not always have the GPF_ATOMIC flag set. Force this flag when inside the larger critical section. dwc_otg: make fiq_split_enable imply fiq_fix_enable Failing to set up the FIQ correctly would result in "IRQ 32: nobody cared" errors in dmesg. dwc_otg: prevent crashes on host port disconnects Fix several issues resulting in crashes or inconsistent state if a Model A root port was disconnected. - Clean up queue heads properly in kill_urbs_in_qh_list by removing the empty QHs from the schedule lists - Set the halt status properly to prevent IRQ handlers from using freed memory - Add fiq_split related cleanup for saved registers - Make microframe scheduling reclaim host channels if active during a disconnect - Abort URBs with -ESHUTDOWN status response, informing device drivers so they respond in a more correct fashion and don't try to resubmit URBs - Prevent IRQ handlers from attempting to handle channel interrupts if the associated URB was dequeued (and the driver state was cleared) dwc_otg: prevent leaking URBs during enqueue A dwc_otg_urb would get leaked if the HCD enqueue function failed for any reason. Free the URB at the appropriate points. dwc_otg: Enable NAK holdoff for control split transactions Certain low-speed devices take a very long time to complete a data or status stage of a control transaction, producing NAK responses until they complete internal processing - the USB2.0 spec limit is up to 500mS. This causes the same type of interrupt storm as seen with USB-serial dongles prior toc8edb238. In certain circumstances, usually while booting, this interrupt storm could cause SD card timeouts. dwc_otg: Fix for occasional lockup on boot when doing a USB reset dwc_otg: Don't issue traffic to LS devices in FS mode Issuing low-speed packets when the root port is in full-speed mode causes the root port to stop responding. Explicitly fail when enqueuing URBs to a LS endpoint on a FS bus. Fix ARM architecture issue with local_irq_restore() If local_fiq_enable() is called before a local_irq_restore(flags) where the flags variable has the F bit set, the FIQ will be erroneously disabled. Fixup arch_local_irq_restore to avoid trampling the F bit in CPSR. Also fix some of the hacks previously implemented for previous dwc_otg incarnations. dwc_otg: fiq_fsm: Base commit for driver rewrite This commit removes the previous FIQ fixes entirely and adds fiq_fsm. This rewrite features much more complete support for split transactions and takes into account several OTG hardware bugs. High-speed isochronous transactions are also capable of being performed by fiq_fsm. All driver options have been removed and replaced with: - dwc_otg.fiq_enable (bool) - dwc_otg.fiq_fsm_enable (bool) - dwc_otg.fiq_fsm_mask (bitmask) - dwc_otg.nak_holdoff (unsigned int) Defaults are specified such that fiq_fsm behaves similarly to the previously implemented FIQ fixes. fiq_fsm: Push error recovery into the FIQ when fiq_fsm is used If the transfer associated with a QTD failed due to a bus error, the HCD would retry the transfer up to 3 times (implementing the USB2.0 three-strikes retry in software). Due to the masking mechanism used by fiq_fsm, it is only possible to pass a single interrupt through to the HCD per-transfer. In this instance host channels would fall off the radar because the error reset would function, but the subsequent channel halt would be lost. Push the error count reset into the FIQ handler. fiq_fsm: Implement timeout mechanism For full-speed endpoints with a large packet size, interrupt latency runs the risk of the FIQ starting a transaction too late in a full-speed frame. If the device is still transmitting data when EOF2 for the downstream frame occurs, the hub will disable the port. This change is not reflected in the hub status endpoint and the device becomes unresponsive. Prevent high-bandwidth transactions from being started too late in a frame. The mechanism is not guaranteed: a combination of bit stuffing and hub latency may still result in a device overrunning. fiq_fsm: fix bounce buffer utilisation for Isochronous OUT Multi-packet isochronous OUT transactions were subject to a few bounday bugs. Fix them. Audio playback is now much more robust: however, an issue stands with devices that have adaptive sinks - ALSA plays samples too fast. dwc_otg: Return full-speed frame numbers in HS mode The frame counter increments on every *microframe* in high-speed mode. Most device drivers expect this number to be in full-speed frames - this caused considerable confusion to e.g. snd_usb_audio which uses the frame counter to estimate the number of samples played. fiq_fsm: save PID on completion of interrupt OUT transfers Also add edge case handling for interrupt transports. Note that for periodic split IN, data toggles are unimplemented in the OTG host hardware - it unconditionally accepts any PID. fiq_fsm: add missing case for fiq_fsm_tt_in_use() Certain combinations of bitrate and endpoint activity could result in a periodic transaction erroneously getting started while the previous Isochronous OUT was still active. fiq_fsm: clear hcintmsk for aborted transactions Prevents the FIQ from erroneously handling interrupts on a timed out channel. fiq_fsm: enable by default fiq_fsm: fix dequeues for non-periodic split transactions If a dequeue happened between the SSPLIT and CSPLIT phases of the transaction, the HCD would never receive an interrupt. fiq_fsm: Disable by default fiq_fsm: Handle HC babble errors The HCTSIZ transfer size field raises a babble interrupt if the counter wraps. Handle the resulting interrupt in this case. dwc_otg: fix interrupt registration for fiq_enable=0 Additionally make the module parameter conditional for wherever hcd->fiq_state is touched. fiq_fsm: Enable by default dwc_otg: Fix various issues with root port and transaction errors Process the host port interrupts correctly (and don't trample them). Root port hotplug now functional again. Fix a few thinkos with the transaction error passthrough for fiq_fsm. fiq_fsm: Implement hack for Split Interrupt transactions Hubs aren't too picky about which endpoint we send Control type split transactions to. By treating Interrupt transfers as Control, it is possible to use the non-periodic queue in the OTG core as well as the non-periodic FIFOs in the hub itself. This massively reduces the microframe exclusivity/contention that periodic split transactions otherwise have to enforce. It goes without saying that this is a fairly egregious USB specification violation, but it works. Original idea by Hans Petter Selasky @ FreeBSD.org. dwc_otg: FIQ support on SMP. Set up FIQ stack and handler on Core 0 only. dwc_otg: introduce fiq_fsm_spin(un|)lock() SMP safety for the FIQ relies on register read-modify write cycles being completed in the correct order. Several places in the DWC code modify registers also touched by the FIQ. Protect these by a bare-bones lock mechanism. This also makes it possible to run the FIQ and IRQ handlers on different cores. fiq_fsm: fix build on bcm2708 and bcm2709 platforms dwc_otg: put some barriers back where they should be for UP bcm2709/dwc_otg: Setup FIQ on core 1 if >1 core active dwc_otg: fixup read-modify-write in critical paths Be more careful about read-modify-write on registers that the FIQ also touches. Guard fiq_fsm_spin_lock with fiq_enable check fiq_fsm: Falling out of the state machine isn't fatal This edge case can be hit if the port is disabled while the FIQ is in the middle of a transaction. Make the effects less severe. Also get rid of the useless return value. squash: dwc_otg: Allow to build without SMP usb: core: make overcurrent messages more prominent Hub overcurrent messages are more serious than "debug". Increase loglevel. usb: dwc_otg: Don't use dma_to_virt() Commit6ce0d20changes dma_to_virt() which breaks this driver. Open code the old dma_to_virt() implementation to work around this. Limit the use of __bus_to_virt() to cases where transfer_buffer_length is set and transfer_buffer is not set. This is done to increase the chance that this driver will also work on ARCH_BCM2835. transfer_buffer should not be NULL if the length is set, but the comment in the code indicates that there are situations where this might happen. drivers/usb/isp1760/isp1760-hcd.c also has a similar comment pointing to a possible: 'usb storage / SCSI bug'. Signed-off-by: Noralf Trønnes <noralf@tronnes.org> dwc_otg: Fix crash when fiq_enable=0 dwc_otg: fiq_fsm: Make high-speed isochronous strided transfers work properly Certain low-bandwidth high-speed USB devices (specialist audio devices, compressed-frame webcams) have packet intervals > 1 microframe. Stride these transfers in the FIQ by using the start-of-frame interrupt to restart the channel at the right time. dwc_otg: Force host mode to fix incorrect compute module boards dwc_otg: Add ARCH_BCM2835 support Signed-off-by: Noralf Trønnes <noralf@tronnes.org> dwc_otg: Simplify FIQ irq number code Dropping ATAGS means we can simplify the FIQ irq number code. Also add error checking on the returned irq number. Signed-off-by: Noralf Trønnes <noralf@tronnes.org> dwc_otg: Remove duplicate gadget probe/unregister function dwc_otg: Properly set the HFIR Douglas Anderson reported: According to the most up to date version of the dwc2 databook, the FRINT field of the HFIR register should be programmed to: * 125 us * (PHY clock freq for HS) - 1 * 1000 us * (PHY clock freq for FS/LS) - 1 This is opposed to older versions of the doc that claimed it should be: * 125 us * (PHY clock freq for HS) * 1000 us * (PHY clock freq for FS/LS) and reported lower timing jitter on a USB analyser dcw_otg: trim xfer length when buffer larger than allocated size is received dwc_otg: Don't free qh align buffers in atomic context dwc_otg: Enable the hack for Split Interrupt transactions by default dwc_otg.fiq_fsm_mask=0xF has long been a suggestion for users with audio stutters or other USB bandwidth issues. So far we are aware of many success stories but no failure caused by this setting. Make it a default to learn more. See: https://www.raspberrypi.org/forums/viewtopic.php?f=28&t=70437 Signed-off-by: popcornmix <popcornmix@gmail.com> dwc_otg: Use kzalloc when suitable dwc_otg: Pass struct device to dma_alloc*() This makes it possible to get the bus address from Device Tree. Signed-off-by: Noralf Trønnes <noralf@tronnes.org> dwc_otg: fix summarize urb->actual_length for isochronous transfers Kernel does not copy input data of ISO transfers to userspace if actual_length is set only in ISO transfers and not summarized in urb->actual_length. Fixes raspberrypi/linux#903 fiq_fsm: Use correct states when starting isoc OUT transfers In fiq_fsm_start_next_periodic() if an isochronous OUT transfer was selected, no regard was given as to whether this was a single-packet transfer or a multi-packet staged transfer. For single-packet transfers, this had the effect of repeatedly sending OUT packets with bogus data and lengths. Eventually if the channel was repeatedly enabled enough times, this would lock up the OTG core and no further bus transfers would happen. Set the FSM state up properly if we select a single-packet transfer. Fixes https://github.com/raspberrypi/linux/issues/1842 dwc_otg: make nak_holdoff work as intended with empty queues If URBs reading from non-periodic split endpoints were dequeued and the last transfer from the endpoint was a NAK handshake, the resulting qh->nak_frame value was stale which would result in unnecessarily long polling intervals for the first subsequent transfer with a fresh URB. Fixup qh->nak_frame in dwc_otg_hcd_urb_dequeue and also guard against a case where a single URB is submitted to the endpoint, a NAK was received on the transfer immediately prior to receiving data and the device subsequently resubmits another URB past the qh->nak_frame interval. Fixes https://github.com/raspberrypi/linux/issues/1709 dwc_otg: fix split transaction data toggle handling around dequeues See https://github.com/raspberrypi/linux/issues/1709 Fix several issues regarding endpoint state when URBs are dequeued - If the HCD is disconnected, flush FIQ-enabled channels properly - Save the data toggle state for bulk endpoints if the last transfer from an endpoint where URBs were dequeued returned a data packet - Reset hc->start_pkt_count properly in assign_and_init_hc() dwc_otg: fix several potential crash sources On root port disconnect events, the host driver state is cleared and in-progress host channels are forcibly stopped. This doesn't play well with the FIQ running in the background, so: - Guard the disconnect callback with both the host spinlock and FIQ spinlock - Move qtd dereference in dwc_otg_handle_hc_fsm() after the early-out so we don't dereference a qtd that has gone away - Turn catch-all BUG()s in dwc_otg_handle_hc_fsm() into warnings. dwc_otg: delete hcd->channel_lock The lock serves no purpose as it is only held while the HCD spinlock is already being held. dwc_otg: remove unnecessary dma-mode channel halts on disconnect interrupt Host channels are already halted in kill_urbs_in_qh_list() with the subsequent interrupt processing behaving as if the URB was dequeued via HCD callback. There's no need to clobber the host channel registers a second time as this exposes races between the driver and host channel resulting in hcd->free_hc_list becoming corrupted. dwcotg: Allow to build without FIQ on ARM64 Signed-off-by: popcornmix <popcornmix@gmail.com> dwc_otg: make periodic scheduling behave properly for FS buses If the root port is in full-speed mode, transfer times at 12mbit/s would be calculated but matched against high-speed quotas. Reinitialise hcd->frame_usecs[i] on each port enable event so that full-speed bandwidth can be tracked sensibly. Also, don't bother using the FIQ for transfers when in full-speed mode - at the slower bus speed, interrupt frequency is reduced by an order of magnitude. Related issue: https://github.com/raspberrypi/linux/issues/2020 dwc_otg: fiq_fsm: Make isochronous compatibility checks work properly Get rid of the spammy printk and local pointer mangling. Also, there is a nominal benefit for using fiq_fsm for isochronous transfers in FS mode (~1.1k IRQs per second vs 2.1k IRQs per second) so remove the root port speed check. dwc_otg: add module parameter int_ep_interval_min Add a module parameter (defaulting to ignored) that clamps the polling rate of high-speed Interrupt endpoints to a minimum microframe interval. The parameter is modifiable at runtime as it is used when activating new endpoints (such as on device connect). dwc_otg: fiq_fsm: Add non-periodic TT exclusivity constraints Certain hub types do not discriminate between pipe direction (IN or OUT) when considering non-periodic transfers. Therefore these hubs get confused if multiple transfers are issued in different directions with the same device address and endpoint number. Constrain queuing non-periodic split transactions so they are performed serially in such cases. Related: https://github.com/raspberrypi/linux/issues/2024 dwc_otg: Fixup change to DRIVER_ATTR interface dwc_otg: Fix compilation warnings Signed-off-by: Phil Elwell <phil@raspberrypi.org> USB_DWCOTG: Disable building dwc_otg as a module (#2265) When dwc_otg is built as a module, build will fail with the following error: ERROR: "DWC_TASK_HI_SCHEDULE" [drivers/usb/host/dwc_otg/dwc_otg.ko] undefined! scripts/Makefile.modpost:91: recipe for target '__modpost' failed make[1]: *** [__modpost] Error 1 Makefile:1199: recipe for target 'modules' failed make: *** [modules] Error 2 Even if the error is solved by including the missing DWC_TASK_HI_SCHEDULE function, the kernel will panic when loading dwc_otg. As a workaround, simply prevent user from building dwc_otg as a module as the current kernel does not support it. See: https://github.com/raspberrypi/linux/issues/2258 Signed-off-by: Malik Olivier Boussejra <malik@boussejra.com> dwc_otg: New timer API dwc_otg: Fix removed ACCESS_ONCE->READ_ONCE dwc_otg: don't unconditionally force host mode in dwc_otg_cil_init() Add the ability to disable force_host_mode for those that want to use dwc_otg in both device and host modes. dwc_otg: Fix a regression when dequeueing isochronous transfers In282bed95(dwc_otg: make nak_holdoff work as intended with empty queues) the dequeue mechanism was changed to leave FIQ-enabled transfers to run to completion - to avoid leaving hub TT buffers with stale packets lying around. This broke FIQ-accelerated isochronous transfers, as this then meant that dozens of transfers were performed after the dequeue function returned. Restore the state machine fence for isochronous transfers. fiq_fsm: rewind DMA pointer for OUT transactions that fail (#2288) See: https://github.com/raspberrypi/linux/issues/2140 dwc_otg: add smp_mb() to prevent driver state corruption on boot Occasional crashes have been seen where the FIQ code dereferences invalid/random pointers immediately after being set up, leading to panic on boot. The crash occurs as the FIQ code races against hcd_init_fiq() and the hcd_init_fiq() code races against the outstanding memory stores from dwc_otg_hcd_init(). Use explicit barriers after touching driver state. usb: dwc_otg: fix memory corruption in dwc_otg driver [Upstream commit51b1b64917] The move from the staging tree to the main tree exposed a longstanding memory corruption bug in the dwc2 driver. The reordering of the driver initialization caused the dwc2 driver to corrupt the initialization data of the sdhci driver on the Raspberry Pi platform, which made the bug show up. The error is in calling to_usb_device(hsotg->dev), since ->dev is not a member of struct usb_device. The easiest fix is to just remove the offending code, since it is not really needed. Thanks to Stephen Warren for tracking down the cause of this. Reported-by: Andre Heider <a.heider@gmail.com> Tested-by: Stephen Warren <swarren@wwwdotorg.org> Signed-off-by: Paul Zimmerman <paulz@synopsys.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> [lukas: port from upstream dwc2 to out-of-tree dwc_otg driver] Signed-off-by: Lukas Wunner <lukas@wunner.de> usb: dwb_otg: Fix unreachable switch statement warning This warning appears with GCC 7.3.0 from toolchains.bootlin.com: ../drivers/usb/host/dwc_otg/dwc_otg_fiq_fsm.c: In function ‘fiq_fsm_update_hs_isoc’: ../drivers/usb/host/dwc_otg/dwc_otg_fiq_fsm.c:595:61: warning: statement will never be executed [-Wswitch-unreachable] st->hctsiz_copy.b.xfersize = nrpackets * st->hcchar_copy.b.mps; ~~~~~~~~~~~~~~~~~^~~~ Signed-off-by: Nathan Chancellor <natechancellor@gmail.com> dwc_otg: fiq_fsm: fix incorrect DMA register offset calculation Rationalise the offset and update all call sites. Fixes https://github.com/raspberrypi/linux/issues/2408
1277 lines
44 KiB
C
1277 lines
44 KiB
C
/* =========================================================================
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* $File: //dwh/usb_iip/dev/software/dwc_common_port_2/dwc_os.h $
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* $Revision: #14 $
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* $Date: 2010/11/04 $
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* $Change: 1621695 $
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*
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* Synopsys Portability Library Software and documentation
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* (hereinafter, "Software") is an Unsupported proprietary work of
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* Synopsys, Inc. unless otherwise expressly agreed to in writing
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* between Synopsys and you.
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*
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* The Software IS NOT an item of Licensed Software or Licensed Product
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* under any End User Software License Agreement or Agreement for
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* Licensed Product with Synopsys or any supplement thereto. You are
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* permitted to use and redistribute this Software in source and binary
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* forms, with or without modification, provided that redistributions
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* of source code must retain this notice. You may not view, use,
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* disclose, copy or distribute this file or any information contained
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* herein except pursuant to this license grant from Synopsys. If you
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* do not agree with this notice, including the disclaimer below, then
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* you are not authorized to use the Software.
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*
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* THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
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* BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL
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* SYNOPSYS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
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* OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
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* USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
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* DAMAGE.
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* ========================================================================= */
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#ifndef _DWC_OS_H_
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#define _DWC_OS_H_
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#ifdef __cplusplus
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extern "C" {
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#endif
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/** @file
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*
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* DWC portability library, low level os-wrapper functions
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*
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*/
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/* These basic types need to be defined by some OS header file or custom header
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* file for your specific target architecture.
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*
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* uint8_t, int8_t, uint16_t, int16_t, uint32_t, int32_t, uint64_t, int64_t
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*
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* Any custom or alternate header file must be added and enabled here.
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*/
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#ifdef DWC_LINUX
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# include <linux/types.h>
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# ifdef CONFIG_DEBUG_MUTEXES
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# include <linux/mutex.h>
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# endif
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# include <linux/spinlock.h>
|
|
# include <linux/errno.h>
|
|
# include <stdarg.h>
|
|
#endif
|
|
|
|
#if defined(DWC_FREEBSD) || defined(DWC_NETBSD)
|
|
# include <os_dep.h>
|
|
#endif
|
|
|
|
|
|
/** @name Primitive Types and Values */
|
|
|
|
/** We define a boolean type for consistency. Can be either YES or NO */
|
|
typedef uint8_t dwc_bool_t;
|
|
#define YES 1
|
|
#define NO 0
|
|
|
|
#ifdef DWC_LINUX
|
|
|
|
/** @name Error Codes */
|
|
#define DWC_E_INVALID EINVAL
|
|
#define DWC_E_NO_MEMORY ENOMEM
|
|
#define DWC_E_NO_DEVICE ENODEV
|
|
#define DWC_E_NOT_SUPPORTED EOPNOTSUPP
|
|
#define DWC_E_TIMEOUT ETIMEDOUT
|
|
#define DWC_E_BUSY EBUSY
|
|
#define DWC_E_AGAIN EAGAIN
|
|
#define DWC_E_RESTART ERESTART
|
|
#define DWC_E_ABORT ECONNABORTED
|
|
#define DWC_E_SHUTDOWN ESHUTDOWN
|
|
#define DWC_E_NO_DATA ENODATA
|
|
#define DWC_E_DISCONNECT ECONNRESET
|
|
#define DWC_E_UNKNOWN EINVAL
|
|
#define DWC_E_NO_STREAM_RES ENOSR
|
|
#define DWC_E_COMMUNICATION ECOMM
|
|
#define DWC_E_OVERFLOW EOVERFLOW
|
|
#define DWC_E_PROTOCOL EPROTO
|
|
#define DWC_E_IN_PROGRESS EINPROGRESS
|
|
#define DWC_E_PIPE EPIPE
|
|
#define DWC_E_IO EIO
|
|
#define DWC_E_NO_SPACE ENOSPC
|
|
|
|
#else
|
|
|
|
/** @name Error Codes */
|
|
#define DWC_E_INVALID 1001
|
|
#define DWC_E_NO_MEMORY 1002
|
|
#define DWC_E_NO_DEVICE 1003
|
|
#define DWC_E_NOT_SUPPORTED 1004
|
|
#define DWC_E_TIMEOUT 1005
|
|
#define DWC_E_BUSY 1006
|
|
#define DWC_E_AGAIN 1007
|
|
#define DWC_E_RESTART 1008
|
|
#define DWC_E_ABORT 1009
|
|
#define DWC_E_SHUTDOWN 1010
|
|
#define DWC_E_NO_DATA 1011
|
|
#define DWC_E_DISCONNECT 2000
|
|
#define DWC_E_UNKNOWN 3000
|
|
#define DWC_E_NO_STREAM_RES 4001
|
|
#define DWC_E_COMMUNICATION 4002
|
|
#define DWC_E_OVERFLOW 4003
|
|
#define DWC_E_PROTOCOL 4004
|
|
#define DWC_E_IN_PROGRESS 4005
|
|
#define DWC_E_PIPE 4006
|
|
#define DWC_E_IO 4007
|
|
#define DWC_E_NO_SPACE 4008
|
|
|
|
#endif
|
|
|
|
|
|
/** @name Tracing/Logging Functions
|
|
*
|
|
* These function provide the capability to add tracing, debugging, and error
|
|
* messages, as well exceptions as assertions. The WUDEV uses these
|
|
* extensively. These could be logged to the main console, the serial port, an
|
|
* internal buffer, etc. These functions could also be no-op if they are too
|
|
* expensive on your system. By default undefining the DEBUG macro already
|
|
* no-ops some of these functions. */
|
|
|
|
/** Returns non-zero if in interrupt context. */
|
|
extern dwc_bool_t DWC_IN_IRQ(void);
|
|
#define dwc_in_irq DWC_IN_IRQ
|
|
|
|
/** Returns "IRQ" if DWC_IN_IRQ is true. */
|
|
static inline char *dwc_irq(void) {
|
|
return DWC_IN_IRQ() ? "IRQ" : "";
|
|
}
|
|
|
|
/** Returns non-zero if in bottom-half context. */
|
|
extern dwc_bool_t DWC_IN_BH(void);
|
|
#define dwc_in_bh DWC_IN_BH
|
|
|
|
/** Returns "BH" if DWC_IN_BH is true. */
|
|
static inline char *dwc_bh(void) {
|
|
return DWC_IN_BH() ? "BH" : "";
|
|
}
|
|
|
|
/**
|
|
* A vprintf() clone. Just call vprintf if you've got it.
|
|
*/
|
|
extern void DWC_VPRINTF(char *format, va_list args);
|
|
#define dwc_vprintf DWC_VPRINTF
|
|
|
|
/**
|
|
* A vsnprintf() clone. Just call vprintf if you've got it.
|
|
*/
|
|
extern int DWC_VSNPRINTF(char *str, int size, char *format, va_list args);
|
|
#define dwc_vsnprintf DWC_VSNPRINTF
|
|
|
|
/**
|
|
* printf() clone. Just call printf if you've go it.
|
|
*/
|
|
extern void DWC_PRINTF(char *format, ...)
|
|
/* This provides compiler level static checking of the parameters if you're
|
|
* using GCC. */
|
|
#ifdef __GNUC__
|
|
__attribute__ ((format(printf, 1, 2)));
|
|
#else
|
|
;
|
|
#endif
|
|
#define dwc_printf DWC_PRINTF
|
|
|
|
/**
|
|
* sprintf() clone. Just call sprintf if you've got it.
|
|
*/
|
|
extern int DWC_SPRINTF(char *string, char *format, ...)
|
|
#ifdef __GNUC__
|
|
__attribute__ ((format(printf, 2, 3)));
|
|
#else
|
|
;
|
|
#endif
|
|
#define dwc_sprintf DWC_SPRINTF
|
|
|
|
/**
|
|
* snprintf() clone. Just call snprintf if you've got it.
|
|
*/
|
|
extern int DWC_SNPRINTF(char *string, int size, char *format, ...)
|
|
#ifdef __GNUC__
|
|
__attribute__ ((format(printf, 3, 4)));
|
|
#else
|
|
;
|
|
#endif
|
|
#define dwc_snprintf DWC_SNPRINTF
|
|
|
|
/**
|
|
* Prints a WARNING message. On systems that don't differentiate between
|
|
* warnings and regular log messages, just print it. Indicates that something
|
|
* may be wrong with the driver. Works like printf().
|
|
*
|
|
* Use the DWC_WARN macro to call this function.
|
|
*/
|
|
extern void __DWC_WARN(char *format, ...)
|
|
#ifdef __GNUC__
|
|
__attribute__ ((format(printf, 1, 2)));
|
|
#else
|
|
;
|
|
#endif
|
|
|
|
/**
|
|
* Prints an error message. On systems that don't differentiate between errors
|
|
* and regular log messages, just print it. Indicates that something went wrong
|
|
* with the driver. Works like printf().
|
|
*
|
|
* Use the DWC_ERROR macro to call this function.
|
|
*/
|
|
extern void __DWC_ERROR(char *format, ...)
|
|
#ifdef __GNUC__
|
|
__attribute__ ((format(printf, 1, 2)));
|
|
#else
|
|
;
|
|
#endif
|
|
|
|
/**
|
|
* Prints an exception error message and takes some user-defined action such as
|
|
* print out a backtrace or trigger a breakpoint. Indicates that something went
|
|
* abnormally wrong with the driver such as programmer error, or other
|
|
* exceptional condition. It should not be ignored so even on systems without
|
|
* printing capability, some action should be taken to notify the developer of
|
|
* it. Works like printf().
|
|
*/
|
|
extern void DWC_EXCEPTION(char *format, ...)
|
|
#ifdef __GNUC__
|
|
__attribute__ ((format(printf, 1, 2)));
|
|
#else
|
|
;
|
|
#endif
|
|
#define dwc_exception DWC_EXCEPTION
|
|
|
|
#ifndef DWC_OTG_DEBUG_LEV
|
|
#define DWC_OTG_DEBUG_LEV 0
|
|
#endif
|
|
|
|
#ifdef DEBUG
|
|
/**
|
|
* Prints out a debug message. Used for logging/trace messages.
|
|
*
|
|
* Use the DWC_DEBUG macro to call this function
|
|
*/
|
|
extern void __DWC_DEBUG(char *format, ...)
|
|
#ifdef __GNUC__
|
|
__attribute__ ((format(printf, 1, 2)));
|
|
#else
|
|
;
|
|
#endif
|
|
#else
|
|
#define __DWC_DEBUG printk
|
|
#endif
|
|
|
|
/**
|
|
* Prints out a Debug message.
|
|
*/
|
|
#define DWC_DEBUG(_format, _args...) __DWC_DEBUG("DEBUG:%s:%s: " _format "\n", \
|
|
__func__, dwc_irq(), ## _args)
|
|
#define dwc_debug DWC_DEBUG
|
|
/**
|
|
* Prints out a Debug message if enabled at compile time.
|
|
*/
|
|
#if DWC_OTG_DEBUG_LEV > 0
|
|
#define DWC_DEBUGC(_format, _args...) DWC_DEBUG(_format, ##_args )
|
|
#else
|
|
#define DWC_DEBUGC(_format, _args...)
|
|
#endif
|
|
#define dwc_debugc DWC_DEBUGC
|
|
/**
|
|
* Prints out an informative message.
|
|
*/
|
|
#define DWC_INFO(_format, _args...) DWC_PRINTF("INFO:%s: " _format "\n", \
|
|
dwc_irq(), ## _args)
|
|
#define dwc_info DWC_INFO
|
|
/**
|
|
* Prints out an informative message if enabled at compile time.
|
|
*/
|
|
#if DWC_OTG_DEBUG_LEV > 1
|
|
#define DWC_INFOC(_format, _args...) DWC_INFO(_format, ##_args )
|
|
#else
|
|
#define DWC_INFOC(_format, _args...)
|
|
#endif
|
|
#define dwc_infoc DWC_INFOC
|
|
/**
|
|
* Prints out a warning message.
|
|
*/
|
|
#define DWC_WARN(_format, _args...) __DWC_WARN("WARN:%s:%s:%d: " _format "\n", \
|
|
dwc_irq(), __func__, __LINE__, ## _args)
|
|
#define dwc_warn DWC_WARN
|
|
/**
|
|
* Prints out an error message.
|
|
*/
|
|
#define DWC_ERROR(_format, _args...) __DWC_ERROR("ERROR:%s:%s:%d: " _format "\n", \
|
|
dwc_irq(), __func__, __LINE__, ## _args)
|
|
#define dwc_error DWC_ERROR
|
|
|
|
#define DWC_PROTO_ERROR(_format, _args...) __DWC_WARN("ERROR:%s:%s:%d: " _format "\n", \
|
|
dwc_irq(), __func__, __LINE__, ## _args)
|
|
#define dwc_proto_error DWC_PROTO_ERROR
|
|
|
|
#ifdef DEBUG
|
|
/** Prints out a exception error message if the _expr expression fails. Disabled
|
|
* if DEBUG is not enabled. */
|
|
#define DWC_ASSERT(_expr, _format, _args...) do { \
|
|
if (!(_expr)) { DWC_EXCEPTION("%s:%s:%d: " _format "\n", dwc_irq(), \
|
|
__FILE__, __LINE__, ## _args); } \
|
|
} while (0)
|
|
#else
|
|
#define DWC_ASSERT(_x...)
|
|
#endif
|
|
#define dwc_assert DWC_ASSERT
|
|
|
|
|
|
/** @name Byte Ordering
|
|
* The following functions are for conversions between processor's byte ordering
|
|
* and specific ordering you want.
|
|
*/
|
|
|
|
/** Converts 32 bit data in CPU byte ordering to little endian. */
|
|
extern uint32_t DWC_CPU_TO_LE32(uint32_t *p);
|
|
#define dwc_cpu_to_le32 DWC_CPU_TO_LE32
|
|
|
|
/** Converts 32 bit data in CPU byte orderint to big endian. */
|
|
extern uint32_t DWC_CPU_TO_BE32(uint32_t *p);
|
|
#define dwc_cpu_to_be32 DWC_CPU_TO_BE32
|
|
|
|
/** Converts 32 bit little endian data to CPU byte ordering. */
|
|
extern uint32_t DWC_LE32_TO_CPU(uint32_t *p);
|
|
#define dwc_le32_to_cpu DWC_LE32_TO_CPU
|
|
|
|
/** Converts 32 bit big endian data to CPU byte ordering. */
|
|
extern uint32_t DWC_BE32_TO_CPU(uint32_t *p);
|
|
#define dwc_be32_to_cpu DWC_BE32_TO_CPU
|
|
|
|
/** Converts 16 bit data in CPU byte ordering to little endian. */
|
|
extern uint16_t DWC_CPU_TO_LE16(uint16_t *p);
|
|
#define dwc_cpu_to_le16 DWC_CPU_TO_LE16
|
|
|
|
/** Converts 16 bit data in CPU byte orderint to big endian. */
|
|
extern uint16_t DWC_CPU_TO_BE16(uint16_t *p);
|
|
#define dwc_cpu_to_be16 DWC_CPU_TO_BE16
|
|
|
|
/** Converts 16 bit little endian data to CPU byte ordering. */
|
|
extern uint16_t DWC_LE16_TO_CPU(uint16_t *p);
|
|
#define dwc_le16_to_cpu DWC_LE16_TO_CPU
|
|
|
|
/** Converts 16 bit bi endian data to CPU byte ordering. */
|
|
extern uint16_t DWC_BE16_TO_CPU(uint16_t *p);
|
|
#define dwc_be16_to_cpu DWC_BE16_TO_CPU
|
|
|
|
|
|
/** @name Register Read/Write
|
|
*
|
|
* The following six functions should be implemented to read/write registers of
|
|
* 32-bit and 64-bit sizes. All modules use this to read/write register values.
|
|
* The reg value is a pointer to the register calculated from the void *base
|
|
* variable passed into the driver when it is started. */
|
|
|
|
#ifdef DWC_LINUX
|
|
/* Linux doesn't need any extra parameters for register read/write, so we
|
|
* just throw away the IO context parameter.
|
|
*/
|
|
/** Reads the content of a 32-bit register. */
|
|
extern uint32_t DWC_READ_REG32(uint32_t volatile *reg);
|
|
#define dwc_read_reg32(_ctx_,_reg_) DWC_READ_REG32(_reg_)
|
|
|
|
/** Reads the content of a 64-bit register. */
|
|
extern uint64_t DWC_READ_REG64(uint64_t volatile *reg);
|
|
#define dwc_read_reg64(_ctx_,_reg_) DWC_READ_REG64(_reg_)
|
|
|
|
/** Writes to a 32-bit register. */
|
|
extern void DWC_WRITE_REG32(uint32_t volatile *reg, uint32_t value);
|
|
#define dwc_write_reg32(_ctx_,_reg_,_val_) DWC_WRITE_REG32(_reg_, _val_)
|
|
|
|
/** Writes to a 64-bit register. */
|
|
extern void DWC_WRITE_REG64(uint64_t volatile *reg, uint64_t value);
|
|
#define dwc_write_reg64(_ctx_,_reg_,_val_) DWC_WRITE_REG64(_reg_, _val_)
|
|
|
|
/**
|
|
* Modify bit values in a register. Using the
|
|
* algorithm: (reg_contents & ~clear_mask) | set_mask.
|
|
*/
|
|
extern void DWC_MODIFY_REG32(uint32_t volatile *reg, uint32_t clear_mask, uint32_t set_mask);
|
|
#define dwc_modify_reg32(_ctx_,_reg_,_cmsk_,_smsk_) DWC_MODIFY_REG32(_reg_,_cmsk_,_smsk_)
|
|
extern void DWC_MODIFY_REG64(uint64_t volatile *reg, uint64_t clear_mask, uint64_t set_mask);
|
|
#define dwc_modify_reg64(_ctx_,_reg_,_cmsk_,_smsk_) DWC_MODIFY_REG64(_reg_,_cmsk_,_smsk_)
|
|
|
|
#endif /* DWC_LINUX */
|
|
|
|
#if defined(DWC_FREEBSD) || defined(DWC_NETBSD)
|
|
typedef struct dwc_ioctx {
|
|
struct device *dev;
|
|
bus_space_tag_t iot;
|
|
bus_space_handle_t ioh;
|
|
} dwc_ioctx_t;
|
|
|
|
/** BSD needs two extra parameters for register read/write, so we pass
|
|
* them in using the IO context parameter.
|
|
*/
|
|
/** Reads the content of a 32-bit register. */
|
|
extern uint32_t DWC_READ_REG32(void *io_ctx, uint32_t volatile *reg);
|
|
#define dwc_read_reg32 DWC_READ_REG32
|
|
|
|
/** Reads the content of a 64-bit register. */
|
|
extern uint64_t DWC_READ_REG64(void *io_ctx, uint64_t volatile *reg);
|
|
#define dwc_read_reg64 DWC_READ_REG64
|
|
|
|
/** Writes to a 32-bit register. */
|
|
extern void DWC_WRITE_REG32(void *io_ctx, uint32_t volatile *reg, uint32_t value);
|
|
#define dwc_write_reg32 DWC_WRITE_REG32
|
|
|
|
/** Writes to a 64-bit register. */
|
|
extern void DWC_WRITE_REG64(void *io_ctx, uint64_t volatile *reg, uint64_t value);
|
|
#define dwc_write_reg64 DWC_WRITE_REG64
|
|
|
|
/**
|
|
* Modify bit values in a register. Using the
|
|
* algorithm: (reg_contents & ~clear_mask) | set_mask.
|
|
*/
|
|
extern void DWC_MODIFY_REG32(void *io_ctx, uint32_t volatile *reg, uint32_t clear_mask, uint32_t set_mask);
|
|
#define dwc_modify_reg32 DWC_MODIFY_REG32
|
|
extern void DWC_MODIFY_REG64(void *io_ctx, uint64_t volatile *reg, uint64_t clear_mask, uint64_t set_mask);
|
|
#define dwc_modify_reg64 DWC_MODIFY_REG64
|
|
|
|
#endif /* DWC_FREEBSD || DWC_NETBSD */
|
|
|
|
/** @cond */
|
|
|
|
/** @name Some convenience MACROS used internally. Define DWC_DEBUG_REGS to log the
|
|
* register writes. */
|
|
|
|
#ifdef DWC_LINUX
|
|
|
|
# ifdef DWC_DEBUG_REGS
|
|
|
|
#define dwc_define_read_write_reg_n(_reg,_container_type) \
|
|
static inline uint32_t dwc_read_##_reg##_n(_container_type *container, int num) { \
|
|
return DWC_READ_REG32(&container->regs->_reg[num]); \
|
|
} \
|
|
static inline void dwc_write_##_reg##_n(_container_type *container, int num, uint32_t data) { \
|
|
DWC_DEBUG("WRITING %8s[%d]: %p: %08x", #_reg, num, \
|
|
&(((uint32_t*)container->regs->_reg)[num]), data); \
|
|
DWC_WRITE_REG32(&(((uint32_t*)container->regs->_reg)[num]), data); \
|
|
}
|
|
|
|
#define dwc_define_read_write_reg(_reg,_container_type) \
|
|
static inline uint32_t dwc_read_##_reg(_container_type *container) { \
|
|
return DWC_READ_REG32(&container->regs->_reg); \
|
|
} \
|
|
static inline void dwc_write_##_reg(_container_type *container, uint32_t data) { \
|
|
DWC_DEBUG("WRITING %11s: %p: %08x", #_reg, &container->regs->_reg, data); \
|
|
DWC_WRITE_REG32(&container->regs->_reg, data); \
|
|
}
|
|
|
|
# else /* DWC_DEBUG_REGS */
|
|
|
|
#define dwc_define_read_write_reg_n(_reg,_container_type) \
|
|
static inline uint32_t dwc_read_##_reg##_n(_container_type *container, int num) { \
|
|
return DWC_READ_REG32(&container->regs->_reg[num]); \
|
|
} \
|
|
static inline void dwc_write_##_reg##_n(_container_type *container, int num, uint32_t data) { \
|
|
DWC_WRITE_REG32(&(((uint32_t*)container->regs->_reg)[num]), data); \
|
|
}
|
|
|
|
#define dwc_define_read_write_reg(_reg,_container_type) \
|
|
static inline uint32_t dwc_read_##_reg(_container_type *container) { \
|
|
return DWC_READ_REG32(&container->regs->_reg); \
|
|
} \
|
|
static inline void dwc_write_##_reg(_container_type *container, uint32_t data) { \
|
|
DWC_WRITE_REG32(&container->regs->_reg, data); \
|
|
}
|
|
|
|
# endif /* DWC_DEBUG_REGS */
|
|
|
|
#endif /* DWC_LINUX */
|
|
|
|
#if defined(DWC_FREEBSD) || defined(DWC_NETBSD)
|
|
|
|
# ifdef DWC_DEBUG_REGS
|
|
|
|
#define dwc_define_read_write_reg_n(_reg,_container_type) \
|
|
static inline uint32_t dwc_read_##_reg##_n(void *io_ctx, _container_type *container, int num) { \
|
|
return DWC_READ_REG32(io_ctx, &container->regs->_reg[num]); \
|
|
} \
|
|
static inline void dwc_write_##_reg##_n(void *io_ctx, _container_type *container, int num, uint32_t data) { \
|
|
DWC_DEBUG("WRITING %8s[%d]: %p: %08x", #_reg, num, \
|
|
&(((uint32_t*)container->regs->_reg)[num]), data); \
|
|
DWC_WRITE_REG32(io_ctx, &(((uint32_t*)container->regs->_reg)[num]), data); \
|
|
}
|
|
|
|
#define dwc_define_read_write_reg(_reg,_container_type) \
|
|
static inline uint32_t dwc_read_##_reg(void *io_ctx, _container_type *container) { \
|
|
return DWC_READ_REG32(io_ctx, &container->regs->_reg); \
|
|
} \
|
|
static inline void dwc_write_##_reg(void *io_ctx, _container_type *container, uint32_t data) { \
|
|
DWC_DEBUG("WRITING %11s: %p: %08x", #_reg, &container->regs->_reg, data); \
|
|
DWC_WRITE_REG32(io_ctx, &container->regs->_reg, data); \
|
|
}
|
|
|
|
# else /* DWC_DEBUG_REGS */
|
|
|
|
#define dwc_define_read_write_reg_n(_reg,_container_type) \
|
|
static inline uint32_t dwc_read_##_reg##_n(void *io_ctx, _container_type *container, int num) { \
|
|
return DWC_READ_REG32(io_ctx, &container->regs->_reg[num]); \
|
|
} \
|
|
static inline void dwc_write_##_reg##_n(void *io_ctx, _container_type *container, int num, uint32_t data) { \
|
|
DWC_WRITE_REG32(io_ctx, &(((uint32_t*)container->regs->_reg)[num]), data); \
|
|
}
|
|
|
|
#define dwc_define_read_write_reg(_reg,_container_type) \
|
|
static inline uint32_t dwc_read_##_reg(void *io_ctx, _container_type *container) { \
|
|
return DWC_READ_REG32(io_ctx, &container->regs->_reg); \
|
|
} \
|
|
static inline void dwc_write_##_reg(void *io_ctx, _container_type *container, uint32_t data) { \
|
|
DWC_WRITE_REG32(io_ctx, &container->regs->_reg, data); \
|
|
}
|
|
|
|
# endif /* DWC_DEBUG_REGS */
|
|
|
|
#endif /* DWC_FREEBSD || DWC_NETBSD */
|
|
|
|
/** @endcond */
|
|
|
|
|
|
#ifdef DWC_CRYPTOLIB
|
|
/** @name Crypto Functions
|
|
*
|
|
* These are the low-level cryptographic functions used by the driver. */
|
|
|
|
/** Perform AES CBC */
|
|
extern int DWC_AES_CBC(uint8_t *message, uint32_t messagelen, uint8_t *key, uint32_t keylen, uint8_t iv[16], uint8_t *out);
|
|
#define dwc_aes_cbc DWC_AES_CBC
|
|
|
|
/** Fill the provided buffer with random bytes. These should be cryptographic grade random numbers. */
|
|
extern void DWC_RANDOM_BYTES(uint8_t *buffer, uint32_t length);
|
|
#define dwc_random_bytes DWC_RANDOM_BYTES
|
|
|
|
/** Perform the SHA-256 hash function */
|
|
extern int DWC_SHA256(uint8_t *message, uint32_t len, uint8_t *out);
|
|
#define dwc_sha256 DWC_SHA256
|
|
|
|
/** Calculated the HMAC-SHA256 */
|
|
extern int DWC_HMAC_SHA256(uint8_t *message, uint32_t messagelen, uint8_t *key, uint32_t keylen, uint8_t *out);
|
|
#define dwc_hmac_sha256 DWC_HMAC_SHA256
|
|
|
|
#endif /* DWC_CRYPTOLIB */
|
|
|
|
|
|
/** @name Memory Allocation
|
|
*
|
|
* These function provide access to memory allocation. There are only 2 DMA
|
|
* functions and 3 Regular memory functions that need to be implemented. None
|
|
* of the memory debugging routines need to be implemented. The allocation
|
|
* routines all ZERO the contents of the memory.
|
|
*
|
|
* Defining DWC_DEBUG_MEMORY turns on memory debugging and statistic gathering.
|
|
* This checks for memory leaks, keeping track of alloc/free pairs. It also
|
|
* keeps track of how much memory the driver is using at any given time. */
|
|
|
|
#define DWC_PAGE_SIZE 4096
|
|
#define DWC_PAGE_OFFSET(addr) (((uint32_t)addr) & 0xfff)
|
|
#define DWC_PAGE_ALIGNED(addr) ((((uint32_t)addr) & 0xfff) == 0)
|
|
|
|
#define DWC_INVALID_DMA_ADDR 0x0
|
|
|
|
#ifdef DWC_LINUX
|
|
/** Type for a DMA address */
|
|
typedef dma_addr_t dwc_dma_t;
|
|
#endif
|
|
|
|
#if defined(DWC_FREEBSD) || defined(DWC_NETBSD)
|
|
typedef bus_addr_t dwc_dma_t;
|
|
#endif
|
|
|
|
#ifdef DWC_FREEBSD
|
|
typedef struct dwc_dmactx {
|
|
struct device *dev;
|
|
bus_dma_tag_t dma_tag;
|
|
bus_dmamap_t dma_map;
|
|
bus_addr_t dma_paddr;
|
|
void *dma_vaddr;
|
|
} dwc_dmactx_t;
|
|
#endif
|
|
|
|
#ifdef DWC_NETBSD
|
|
typedef struct dwc_dmactx {
|
|
struct device *dev;
|
|
bus_dma_tag_t dma_tag;
|
|
bus_dmamap_t dma_map;
|
|
bus_dma_segment_t segs[1];
|
|
int nsegs;
|
|
bus_addr_t dma_paddr;
|
|
void *dma_vaddr;
|
|
} dwc_dmactx_t;
|
|
#endif
|
|
|
|
/* @todo these functions will be added in the future */
|
|
#if 0
|
|
/**
|
|
* Creates a DMA pool from which you can allocate DMA buffers. Buffers
|
|
* allocated from this pool will be guaranteed to meet the size, alignment, and
|
|
* boundary requirements specified.
|
|
*
|
|
* @param[in] size Specifies the size of the buffers that will be allocated from
|
|
* this pool.
|
|
* @param[in] align Specifies the byte alignment requirements of the buffers
|
|
* allocated from this pool. Must be a power of 2.
|
|
* @param[in] boundary Specifies the N-byte boundary that buffers allocated from
|
|
* this pool must not cross.
|
|
*
|
|
* @returns A pointer to an internal opaque structure which is not to be
|
|
* accessed outside of these library functions. Use this handle to specify
|
|
* which pools to allocate/free DMA buffers from and also to destroy the pool,
|
|
* when you are done with it.
|
|
*/
|
|
extern dwc_pool_t *DWC_DMA_POOL_CREATE(uint32_t size, uint32_t align, uint32_t boundary);
|
|
|
|
/**
|
|
* Destroy a DMA pool. All buffers allocated from that pool must be freed first.
|
|
*/
|
|
extern void DWC_DMA_POOL_DESTROY(dwc_pool_t *pool);
|
|
|
|
/**
|
|
* Allocate a buffer from the specified DMA pool and zeros its contents.
|
|
*/
|
|
extern void *DWC_DMA_POOL_ALLOC(dwc_pool_t *pool, uint64_t *dma_addr);
|
|
|
|
/**
|
|
* Free a previously allocated buffer from the DMA pool.
|
|
*/
|
|
extern void DWC_DMA_POOL_FREE(dwc_pool_t *pool, void *vaddr, void *daddr);
|
|
#endif
|
|
|
|
/** Allocates a DMA capable buffer and zeroes its contents. */
|
|
extern void *__DWC_DMA_ALLOC(void *dma_ctx, uint32_t size, dwc_dma_t *dma_addr);
|
|
|
|
/** Allocates a DMA capable buffer and zeroes its contents in atomic contest */
|
|
extern void *__DWC_DMA_ALLOC_ATOMIC(void *dma_ctx, uint32_t size, dwc_dma_t *dma_addr);
|
|
|
|
/** Frees a previously allocated buffer. */
|
|
extern void __DWC_DMA_FREE(void *dma_ctx, uint32_t size, void *virt_addr, dwc_dma_t dma_addr);
|
|
|
|
/** Allocates a block of memory and zeroes its contents. */
|
|
extern void *__DWC_ALLOC(void *mem_ctx, uint32_t size);
|
|
|
|
/** Allocates a block of memory and zeroes its contents, in an atomic manner
|
|
* which can be used inside interrupt context. The size should be sufficiently
|
|
* small, a few KB at most, such that failures are not likely to occur. Can just call
|
|
* __DWC_ALLOC if it is atomic. */
|
|
extern void *__DWC_ALLOC_ATOMIC(void *mem_ctx, uint32_t size);
|
|
|
|
/** Frees a previously allocated buffer. */
|
|
extern void __DWC_FREE(void *mem_ctx, void *addr);
|
|
|
|
#ifndef DWC_DEBUG_MEMORY
|
|
|
|
#define DWC_ALLOC(_size_) __DWC_ALLOC(NULL, _size_)
|
|
#define DWC_ALLOC_ATOMIC(_size_) __DWC_ALLOC_ATOMIC(NULL, _size_)
|
|
#define DWC_FREE(_addr_) __DWC_FREE(NULL, _addr_)
|
|
|
|
# ifdef DWC_LINUX
|
|
#define DWC_DMA_ALLOC(_dev, _size_, _dma_) __DWC_DMA_ALLOC(_dev, _size_, _dma_)
|
|
#define DWC_DMA_ALLOC_ATOMIC(_dev, _size_, _dma_) __DWC_DMA_ALLOC_ATOMIC(_dev, _size_, _dma_)
|
|
#define DWC_DMA_FREE(_dev, _size_,_virt_, _dma_) __DWC_DMA_FREE(_dev, _size_, _virt_, _dma_)
|
|
# endif
|
|
|
|
# if defined(DWC_FREEBSD) || defined(DWC_NETBSD)
|
|
#define DWC_DMA_ALLOC __DWC_DMA_ALLOC
|
|
#define DWC_DMA_FREE __DWC_DMA_FREE
|
|
# endif
|
|
extern void *dwc_dma_alloc_atomic_debug(uint32_t size, dwc_dma_t *dma_addr, char const *func, int line);
|
|
|
|
#else /* DWC_DEBUG_MEMORY */
|
|
|
|
extern void *dwc_alloc_debug(void *mem_ctx, uint32_t size, char const *func, int line);
|
|
extern void *dwc_alloc_atomic_debug(void *mem_ctx, uint32_t size, char const *func, int line);
|
|
extern void dwc_free_debug(void *mem_ctx, void *addr, char const *func, int line);
|
|
extern void *dwc_dma_alloc_debug(void *dma_ctx, uint32_t size, dwc_dma_t *dma_addr,
|
|
char const *func, int line);
|
|
extern void *dwc_dma_alloc_atomic_debug(void *dma_ctx, uint32_t size, dwc_dma_t *dma_addr,
|
|
char const *func, int line);
|
|
extern void dwc_dma_free_debug(void *dma_ctx, uint32_t size, void *virt_addr,
|
|
dwc_dma_t dma_addr, char const *func, int line);
|
|
|
|
extern int dwc_memory_debug_start(void *mem_ctx);
|
|
extern void dwc_memory_debug_stop(void);
|
|
extern void dwc_memory_debug_report(void);
|
|
|
|
#define DWC_ALLOC(_size_) dwc_alloc_debug(NULL, _size_, __func__, __LINE__)
|
|
#define DWC_ALLOC_ATOMIC(_size_) dwc_alloc_atomic_debug(NULL, _size_, \
|
|
__func__, __LINE__)
|
|
#define DWC_FREE(_addr_) dwc_free_debug(NULL, _addr_, __func__, __LINE__)
|
|
|
|
# ifdef DWC_LINUX
|
|
#define DWC_DMA_ALLOC(_dev, _size_, _dma_) \
|
|
dwc_dma_alloc_debug(_dev, _size_, _dma_, __func__, __LINE__)
|
|
#define DWC_DMA_ALLOC_ATOMIC(_dev, _size_, _dma_) \
|
|
dwc_dma_alloc_atomic_debug(_dev, _size_, _dma_, __func__, __LINE__)
|
|
#define DWC_DMA_FREE(_dev, _size_, _virt_, _dma_) \
|
|
dwc_dma_free_debug(_dev, _size_, _virt_, _dma_, __func__, __LINE__)
|
|
# endif
|
|
|
|
# if defined(DWC_FREEBSD) || defined(DWC_NETBSD)
|
|
#define DWC_DMA_ALLOC(_ctx_,_size_,_dma_) dwc_dma_alloc_debug(_ctx_, _size_, \
|
|
_dma_, __func__, __LINE__)
|
|
#define DWC_DMA_FREE(_ctx_,_size_,_virt_,_dma_) dwc_dma_free_debug(_ctx_, _size_, \
|
|
_virt_, _dma_, __func__, __LINE__)
|
|
# endif
|
|
|
|
#endif /* DWC_DEBUG_MEMORY */
|
|
|
|
#define dwc_alloc(_ctx_,_size_) DWC_ALLOC(_size_)
|
|
#define dwc_alloc_atomic(_ctx_,_size_) DWC_ALLOC_ATOMIC(_size_)
|
|
#define dwc_free(_ctx_,_addr_) DWC_FREE(_addr_)
|
|
|
|
#ifdef DWC_LINUX
|
|
/* Linux doesn't need any extra parameters for DMA buffer allocation, so we
|
|
* just throw away the DMA context parameter.
|
|
*/
|
|
#define dwc_dma_alloc(_ctx_,_size_,_dma_) DWC_DMA_ALLOC(_size_, _dma_)
|
|
#define dwc_dma_alloc_atomic(_ctx_,_size_,_dma_) DWC_DMA_ALLOC_ATOMIC(_size_, _dma_)
|
|
#define dwc_dma_free(_ctx_,_size_,_virt_,_dma_) DWC_DMA_FREE(_size_, _virt_, _dma_)
|
|
#endif
|
|
|
|
#if defined(DWC_FREEBSD) || defined(DWC_NETBSD)
|
|
/** BSD needs several extra parameters for DMA buffer allocation, so we pass
|
|
* them in using the DMA context parameter.
|
|
*/
|
|
#define dwc_dma_alloc DWC_DMA_ALLOC
|
|
#define dwc_dma_free DWC_DMA_FREE
|
|
#endif
|
|
|
|
|
|
/** @name Memory and String Processing */
|
|
|
|
/** memset() clone */
|
|
extern void *DWC_MEMSET(void *dest, uint8_t byte, uint32_t size);
|
|
#define dwc_memset DWC_MEMSET
|
|
|
|
/** memcpy() clone */
|
|
extern void *DWC_MEMCPY(void *dest, void const *src, uint32_t size);
|
|
#define dwc_memcpy DWC_MEMCPY
|
|
|
|
/** memmove() clone */
|
|
extern void *DWC_MEMMOVE(void *dest, void *src, uint32_t size);
|
|
#define dwc_memmove DWC_MEMMOVE
|
|
|
|
/** memcmp() clone */
|
|
extern int DWC_MEMCMP(void *m1, void *m2, uint32_t size);
|
|
#define dwc_memcmp DWC_MEMCMP
|
|
|
|
/** strcmp() clone */
|
|
extern int DWC_STRCMP(void *s1, void *s2);
|
|
#define dwc_strcmp DWC_STRCMP
|
|
|
|
/** strncmp() clone */
|
|
extern int DWC_STRNCMP(void *s1, void *s2, uint32_t size);
|
|
#define dwc_strncmp DWC_STRNCMP
|
|
|
|
/** strlen() clone, for NULL terminated ASCII strings */
|
|
extern int DWC_STRLEN(char const *str);
|
|
#define dwc_strlen DWC_STRLEN
|
|
|
|
/** strcpy() clone, for NULL terminated ASCII strings */
|
|
extern char *DWC_STRCPY(char *to, const char *from);
|
|
#define dwc_strcpy DWC_STRCPY
|
|
|
|
/** strdup() clone. If you wish to use memory allocation debugging, this
|
|
* implementation of strdup should use the DWC_* memory routines instead of
|
|
* calling a predefined strdup. Otherwise the memory allocated by this routine
|
|
* will not be seen by the debugging routines. */
|
|
extern char *DWC_STRDUP(char const *str);
|
|
#define dwc_strdup(_ctx_,_str_) DWC_STRDUP(_str_)
|
|
|
|
/** NOT an atoi() clone. Read the description carefully. Returns an integer
|
|
* converted from the string str in base 10 unless the string begins with a "0x"
|
|
* in which case it is base 16. String must be a NULL terminated sequence of
|
|
* ASCII characters and may optionally begin with whitespace, a + or -, and a
|
|
* "0x" prefix if base 16. The remaining characters must be valid digits for
|
|
* the number and end with a NULL character. If any invalid characters are
|
|
* encountered or it returns with a negative error code and the results of the
|
|
* conversion are undefined. On sucess it returns 0. Overflow conditions are
|
|
* undefined. An example implementation using atoi() can be referenced from the
|
|
* Linux implementation. */
|
|
extern int DWC_ATOI(const char *str, int32_t *value);
|
|
#define dwc_atoi DWC_ATOI
|
|
|
|
/** Same as above but for unsigned. */
|
|
extern int DWC_ATOUI(const char *str, uint32_t *value);
|
|
#define dwc_atoui DWC_ATOUI
|
|
|
|
#ifdef DWC_UTFLIB
|
|
/** This routine returns a UTF16LE unicode encoded string from a UTF8 string. */
|
|
extern int DWC_UTF8_TO_UTF16LE(uint8_t const *utf8string, uint16_t *utf16string, unsigned len);
|
|
#define dwc_utf8_to_utf16le DWC_UTF8_TO_UTF16LE
|
|
#endif
|
|
|
|
|
|
/** @name Wait queues
|
|
*
|
|
* Wait queues provide a means of synchronizing between threads or processes. A
|
|
* process can block on a waitq if some condition is not true, waiting for it to
|
|
* become true. When the waitq is triggered all waiting process will get
|
|
* unblocked and the condition will be check again. Waitqs should be triggered
|
|
* every time a condition can potentially change.*/
|
|
struct dwc_waitq;
|
|
|
|
/** Type for a waitq */
|
|
typedef struct dwc_waitq dwc_waitq_t;
|
|
|
|
/** The type of waitq condition callback function. This is called every time
|
|
* condition is evaluated. */
|
|
typedef int (*dwc_waitq_condition_t)(void *data);
|
|
|
|
/** Allocate a waitq */
|
|
extern dwc_waitq_t *DWC_WAITQ_ALLOC(void);
|
|
#define dwc_waitq_alloc(_ctx_) DWC_WAITQ_ALLOC()
|
|
|
|
/** Free a waitq */
|
|
extern void DWC_WAITQ_FREE(dwc_waitq_t *wq);
|
|
#define dwc_waitq_free DWC_WAITQ_FREE
|
|
|
|
/** Check the condition and if it is false, block on the waitq. When unblocked, check the
|
|
* condition again. The function returns when the condition becomes true. The return value
|
|
* is 0 on condition true, DWC_WAITQ_ABORTED on abort or killed, or DWC_WAITQ_UNKNOWN on error. */
|
|
extern int32_t DWC_WAITQ_WAIT(dwc_waitq_t *wq, dwc_waitq_condition_t cond, void *data);
|
|
#define dwc_waitq_wait DWC_WAITQ_WAIT
|
|
|
|
/** Check the condition and if it is false, block on the waitq. When unblocked,
|
|
* check the condition again. The function returns when the condition become
|
|
* true or the timeout has passed. The return value is 0 on condition true or
|
|
* DWC_TIMED_OUT on timeout, or DWC_WAITQ_ABORTED, or DWC_WAITQ_UNKNOWN on
|
|
* error. */
|
|
extern int32_t DWC_WAITQ_WAIT_TIMEOUT(dwc_waitq_t *wq, dwc_waitq_condition_t cond,
|
|
void *data, int32_t msecs);
|
|
#define dwc_waitq_wait_timeout DWC_WAITQ_WAIT_TIMEOUT
|
|
|
|
/** Trigger a waitq, unblocking all processes. This should be called whenever a condition
|
|
* has potentially changed. */
|
|
extern void DWC_WAITQ_TRIGGER(dwc_waitq_t *wq);
|
|
#define dwc_waitq_trigger DWC_WAITQ_TRIGGER
|
|
|
|
/** Unblock all processes waiting on the waitq with an ABORTED result. */
|
|
extern void DWC_WAITQ_ABORT(dwc_waitq_t *wq);
|
|
#define dwc_waitq_abort DWC_WAITQ_ABORT
|
|
|
|
|
|
/** @name Threads
|
|
*
|
|
* A thread must be explicitly stopped. It must check DWC_THREAD_SHOULD_STOP
|
|
* whenever it is woken up, and then return. The DWC_THREAD_STOP function
|
|
* returns the value from the thread.
|
|
*/
|
|
|
|
struct dwc_thread;
|
|
|
|
/** Type for a thread */
|
|
typedef struct dwc_thread dwc_thread_t;
|
|
|
|
/** The thread function */
|
|
typedef int (*dwc_thread_function_t)(void *data);
|
|
|
|
/** Create a thread and start it running the thread_function. Returns a handle
|
|
* to the thread */
|
|
extern dwc_thread_t *DWC_THREAD_RUN(dwc_thread_function_t func, char *name, void *data);
|
|
#define dwc_thread_run(_ctx_,_func_,_name_,_data_) DWC_THREAD_RUN(_func_, _name_, _data_)
|
|
|
|
/** Stops a thread. Return the value returned by the thread. Or will return
|
|
* DWC_ABORT if the thread never started. */
|
|
extern int DWC_THREAD_STOP(dwc_thread_t *thread);
|
|
#define dwc_thread_stop DWC_THREAD_STOP
|
|
|
|
/** Signifies to the thread that it must stop. */
|
|
#ifdef DWC_LINUX
|
|
/* Linux doesn't need any parameters for kthread_should_stop() */
|
|
extern dwc_bool_t DWC_THREAD_SHOULD_STOP(void);
|
|
#define dwc_thread_should_stop(_thrd_) DWC_THREAD_SHOULD_STOP()
|
|
|
|
/* No thread_exit function in Linux */
|
|
#define dwc_thread_exit(_thrd_)
|
|
#endif
|
|
|
|
#if defined(DWC_FREEBSD) || defined(DWC_NETBSD)
|
|
/** BSD needs the thread pointer for kthread_suspend_check() */
|
|
extern dwc_bool_t DWC_THREAD_SHOULD_STOP(dwc_thread_t *thread);
|
|
#define dwc_thread_should_stop DWC_THREAD_SHOULD_STOP
|
|
|
|
/** The thread must call this to exit. */
|
|
extern void DWC_THREAD_EXIT(dwc_thread_t *thread);
|
|
#define dwc_thread_exit DWC_THREAD_EXIT
|
|
#endif
|
|
|
|
|
|
/** @name Work queues
|
|
*
|
|
* Workqs are used to queue a callback function to be called at some later time,
|
|
* in another thread. */
|
|
struct dwc_workq;
|
|
|
|
/** Type for a workq */
|
|
typedef struct dwc_workq dwc_workq_t;
|
|
|
|
/** The type of the callback function to be called. */
|
|
typedef void (*dwc_work_callback_t)(void *data);
|
|
|
|
/** Allocate a workq */
|
|
extern dwc_workq_t *DWC_WORKQ_ALLOC(char *name);
|
|
#define dwc_workq_alloc(_ctx_,_name_) DWC_WORKQ_ALLOC(_name_)
|
|
|
|
/** Free a workq. All work must be completed before being freed. */
|
|
extern void DWC_WORKQ_FREE(dwc_workq_t *workq);
|
|
#define dwc_workq_free DWC_WORKQ_FREE
|
|
|
|
/** Schedule a callback on the workq, passing in data. The function will be
|
|
* scheduled at some later time. */
|
|
extern void DWC_WORKQ_SCHEDULE(dwc_workq_t *workq, dwc_work_callback_t cb,
|
|
void *data, char *format, ...)
|
|
#ifdef __GNUC__
|
|
__attribute__ ((format(printf, 4, 5)));
|
|
#else
|
|
;
|
|
#endif
|
|
#define dwc_workq_schedule DWC_WORKQ_SCHEDULE
|
|
|
|
/** Schedule a callback on the workq, that will be called until at least
|
|
* given number miliseconds have passed. */
|
|
extern void DWC_WORKQ_SCHEDULE_DELAYED(dwc_workq_t *workq, dwc_work_callback_t cb,
|
|
void *data, uint32_t time, char *format, ...)
|
|
#ifdef __GNUC__
|
|
__attribute__ ((format(printf, 5, 6)));
|
|
#else
|
|
;
|
|
#endif
|
|
#define dwc_workq_schedule_delayed DWC_WORKQ_SCHEDULE_DELAYED
|
|
|
|
/** The number of processes in the workq */
|
|
extern int DWC_WORKQ_PENDING(dwc_workq_t *workq);
|
|
#define dwc_workq_pending DWC_WORKQ_PENDING
|
|
|
|
/** Blocks until all the work in the workq is complete or timed out. Returns <
|
|
* 0 on timeout. */
|
|
extern int DWC_WORKQ_WAIT_WORK_DONE(dwc_workq_t *workq, int timeout);
|
|
#define dwc_workq_wait_work_done DWC_WORKQ_WAIT_WORK_DONE
|
|
|
|
|
|
/** @name Tasklets
|
|
*
|
|
*/
|
|
struct dwc_tasklet;
|
|
|
|
/** Type for a tasklet */
|
|
typedef struct dwc_tasklet dwc_tasklet_t;
|
|
|
|
/** The type of the callback function to be called */
|
|
typedef void (*dwc_tasklet_callback_t)(void *data);
|
|
|
|
/** Allocates a tasklet */
|
|
extern dwc_tasklet_t *DWC_TASK_ALLOC(char *name, dwc_tasklet_callback_t cb, void *data);
|
|
#define dwc_task_alloc(_ctx_,_name_,_cb_,_data_) DWC_TASK_ALLOC(_name_, _cb_, _data_)
|
|
|
|
/** Frees a tasklet */
|
|
extern void DWC_TASK_FREE(dwc_tasklet_t *task);
|
|
#define dwc_task_free DWC_TASK_FREE
|
|
|
|
/** Schedules a tasklet to run */
|
|
extern void DWC_TASK_SCHEDULE(dwc_tasklet_t *task);
|
|
#define dwc_task_schedule DWC_TASK_SCHEDULE
|
|
|
|
extern void DWC_TASK_HI_SCHEDULE(dwc_tasklet_t *task);
|
|
#define dwc_task_hi_schedule DWC_TASK_HI_SCHEDULE
|
|
|
|
/** @name Timer
|
|
*
|
|
* Callbacks must be small and atomic.
|
|
*/
|
|
struct dwc_timer;
|
|
|
|
/** Type for a timer */
|
|
typedef struct dwc_timer dwc_timer_t;
|
|
|
|
/** The type of the callback function to be called */
|
|
typedef void (*dwc_timer_callback_t)(void *data);
|
|
|
|
/** Allocates a timer */
|
|
extern dwc_timer_t *DWC_TIMER_ALLOC(char *name, dwc_timer_callback_t cb, void *data);
|
|
#define dwc_timer_alloc(_ctx_,_name_,_cb_,_data_) DWC_TIMER_ALLOC(_name_,_cb_,_data_)
|
|
|
|
/** Frees a timer */
|
|
extern void DWC_TIMER_FREE(dwc_timer_t *timer);
|
|
#define dwc_timer_free DWC_TIMER_FREE
|
|
|
|
/** Schedules the timer to run at time ms from now. And will repeat at every
|
|
* repeat_interval msec therafter
|
|
*
|
|
* Modifies a timer that is still awaiting execution to a new expiration time.
|
|
* The mod_time is added to the old time. */
|
|
extern void DWC_TIMER_SCHEDULE(dwc_timer_t *timer, uint32_t time);
|
|
#define dwc_timer_schedule DWC_TIMER_SCHEDULE
|
|
|
|
/** Disables the timer from execution. */
|
|
extern void DWC_TIMER_CANCEL(dwc_timer_t *timer);
|
|
#define dwc_timer_cancel DWC_TIMER_CANCEL
|
|
|
|
|
|
/** @name Spinlocks
|
|
*
|
|
* These locks are used when the work between the lock/unlock is atomic and
|
|
* short. Interrupts are also disabled during the lock/unlock and thus they are
|
|
* suitable to lock between interrupt/non-interrupt context. They also lock
|
|
* between processes if you have multiple CPUs or Preemption. If you don't have
|
|
* multiple CPUS or Preemption, then the you can simply implement the
|
|
* DWC_SPINLOCK and DWC_SPINUNLOCK to disable and enable interrupts. Because
|
|
* the work between the lock/unlock is atomic, the process context will never
|
|
* change, and so you never have to lock between processes. */
|
|
|
|
struct dwc_spinlock;
|
|
|
|
/** Type for a spinlock */
|
|
typedef struct dwc_spinlock dwc_spinlock_t;
|
|
|
|
/** Type for the 'flags' argument to spinlock funtions */
|
|
typedef unsigned long dwc_irqflags_t;
|
|
|
|
/** Returns an initialized lock variable. This function should allocate and
|
|
* initialize the OS-specific data structure used for locking. This data
|
|
* structure is to be used for the DWC_LOCK and DWC_UNLOCK functions and should
|
|
* be freed by the DWC_FREE_LOCK when it is no longer used.
|
|
*
|
|
* For Linux Spinlock Debugging make it macro because the debugging routines use
|
|
* the symbol name to determine recursive locking. Using a wrapper function
|
|
* makes it falsely think recursive locking occurs. */
|
|
#if defined(DWC_LINUX) && defined(CONFIG_DEBUG_SPINLOCK)
|
|
#define DWC_SPINLOCK_ALLOC_LINUX_DEBUG(lock) ({ \
|
|
lock = DWC_ALLOC(sizeof(spinlock_t)); \
|
|
if (lock) { \
|
|
spin_lock_init((spinlock_t *)lock); \
|
|
} \
|
|
})
|
|
#else
|
|
extern dwc_spinlock_t *DWC_SPINLOCK_ALLOC(void);
|
|
#define dwc_spinlock_alloc(_ctx_) DWC_SPINLOCK_ALLOC()
|
|
#endif
|
|
|
|
/** Frees an initialized lock variable. */
|
|
extern void DWC_SPINLOCK_FREE(dwc_spinlock_t *lock);
|
|
#define dwc_spinlock_free(_ctx_,_lock_) DWC_SPINLOCK_FREE(_lock_)
|
|
|
|
/** Disables interrupts and blocks until it acquires the lock.
|
|
*
|
|
* @param lock Pointer to the spinlock.
|
|
* @param flags Unsigned long for irq flags storage.
|
|
*/
|
|
extern void DWC_SPINLOCK_IRQSAVE(dwc_spinlock_t *lock, dwc_irqflags_t *flags);
|
|
#define dwc_spinlock_irqsave DWC_SPINLOCK_IRQSAVE
|
|
|
|
/** Re-enables the interrupt and releases the lock.
|
|
*
|
|
* @param lock Pointer to the spinlock.
|
|
* @param flags Unsigned long for irq flags storage. Must be the same as was
|
|
* passed into DWC_LOCK.
|
|
*/
|
|
extern void DWC_SPINUNLOCK_IRQRESTORE(dwc_spinlock_t *lock, dwc_irqflags_t flags);
|
|
#define dwc_spinunlock_irqrestore DWC_SPINUNLOCK_IRQRESTORE
|
|
|
|
/** Blocks until it acquires the lock.
|
|
*
|
|
* @param lock Pointer to the spinlock.
|
|
*/
|
|
extern void DWC_SPINLOCK(dwc_spinlock_t *lock);
|
|
#define dwc_spinlock DWC_SPINLOCK
|
|
|
|
/** Releases the lock.
|
|
*
|
|
* @param lock Pointer to the spinlock.
|
|
*/
|
|
extern void DWC_SPINUNLOCK(dwc_spinlock_t *lock);
|
|
#define dwc_spinunlock DWC_SPINUNLOCK
|
|
|
|
|
|
/** @name Mutexes
|
|
*
|
|
* Unlike spinlocks Mutexes lock only between processes and the work between the
|
|
* lock/unlock CAN block, therefore it CANNOT be called from interrupt context.
|
|
*/
|
|
|
|
struct dwc_mutex;
|
|
|
|
/** Type for a mutex */
|
|
typedef struct dwc_mutex dwc_mutex_t;
|
|
|
|
/* For Linux Mutex Debugging make it inline because the debugging routines use
|
|
* the symbol to determine recursive locking. This makes it falsely think
|
|
* recursive locking occurs. */
|
|
#if defined(DWC_LINUX) && defined(CONFIG_DEBUG_MUTEXES)
|
|
#define DWC_MUTEX_ALLOC_LINUX_DEBUG(__mutexp) ({ \
|
|
__mutexp = (dwc_mutex_t *)DWC_ALLOC(sizeof(struct mutex)); \
|
|
mutex_init((struct mutex *)__mutexp); \
|
|
})
|
|
#endif
|
|
|
|
/** Allocate a mutex */
|
|
extern dwc_mutex_t *DWC_MUTEX_ALLOC(void);
|
|
#define dwc_mutex_alloc(_ctx_) DWC_MUTEX_ALLOC()
|
|
|
|
/* For memory leak debugging when using Linux Mutex Debugging */
|
|
#if defined(DWC_LINUX) && defined(CONFIG_DEBUG_MUTEXES)
|
|
#define DWC_MUTEX_FREE(__mutexp) do { \
|
|
mutex_destroy((struct mutex *)__mutexp); \
|
|
DWC_FREE(__mutexp); \
|
|
} while(0)
|
|
#else
|
|
/** Free a mutex */
|
|
extern void DWC_MUTEX_FREE(dwc_mutex_t *mutex);
|
|
#define dwc_mutex_free(_ctx_,_mutex_) DWC_MUTEX_FREE(_mutex_)
|
|
#endif
|
|
|
|
/** Lock a mutex */
|
|
extern void DWC_MUTEX_LOCK(dwc_mutex_t *mutex);
|
|
#define dwc_mutex_lock DWC_MUTEX_LOCK
|
|
|
|
/** Non-blocking lock returns 1 on successful lock. */
|
|
extern int DWC_MUTEX_TRYLOCK(dwc_mutex_t *mutex);
|
|
#define dwc_mutex_trylock DWC_MUTEX_TRYLOCK
|
|
|
|
/** Unlock a mutex */
|
|
extern void DWC_MUTEX_UNLOCK(dwc_mutex_t *mutex);
|
|
#define dwc_mutex_unlock DWC_MUTEX_UNLOCK
|
|
|
|
|
|
/** @name Time */
|
|
|
|
/** Microsecond delay.
|
|
*
|
|
* @param usecs Microseconds to delay.
|
|
*/
|
|
extern void DWC_UDELAY(uint32_t usecs);
|
|
#define dwc_udelay DWC_UDELAY
|
|
|
|
/** Millisecond delay.
|
|
*
|
|
* @param msecs Milliseconds to delay.
|
|
*/
|
|
extern void DWC_MDELAY(uint32_t msecs);
|
|
#define dwc_mdelay DWC_MDELAY
|
|
|
|
/** Non-busy waiting.
|
|
* Sleeps for specified number of milliseconds.
|
|
*
|
|
* @param msecs Milliseconds to sleep.
|
|
*/
|
|
extern void DWC_MSLEEP(uint32_t msecs);
|
|
#define dwc_msleep DWC_MSLEEP
|
|
|
|
/**
|
|
* Returns number of milliseconds since boot.
|
|
*/
|
|
extern uint32_t DWC_TIME(void);
|
|
#define dwc_time DWC_TIME
|
|
|
|
|
|
|
|
|
|
/* @mainpage DWC Portability and Common Library
|
|
*
|
|
* This is the documentation for the DWC Portability and Common Library.
|
|
*
|
|
* @section intro Introduction
|
|
*
|
|
* The DWC Portability library consists of wrapper calls and data structures to
|
|
* all low-level functions which are typically provided by the OS. The WUDEV
|
|
* driver uses only these functions. In order to port the WUDEV driver, only
|
|
* the functions in this library need to be re-implemented, with the same
|
|
* behavior as documented here.
|
|
*
|
|
* The Common library consists of higher level functions, which rely only on
|
|
* calling the functions from the DWC Portability library. These common
|
|
* routines are shared across modules. Some of the common libraries need to be
|
|
* used directly by the driver programmer when porting WUDEV. Such as the
|
|
* parameter and notification libraries.
|
|
*
|
|
* @section low Portability Library OS Wrapper Functions
|
|
*
|
|
* Any function starting with DWC and in all CAPS is a low-level OS-wrapper that
|
|
* needs to be implemented when porting, for example DWC_MUTEX_ALLOC(). All of
|
|
* these functions are included in the dwc_os.h file.
|
|
*
|
|
* There are many functions here covering a wide array of OS services. Please
|
|
* see dwc_os.h for details, and implementation notes for each function.
|
|
*
|
|
* @section common Common Library Functions
|
|
*
|
|
* Any function starting with dwc and in all lowercase is a common library
|
|
* routine. These functions have a portable implementation and do not need to
|
|
* be reimplemented when porting. The common routines can be used by any
|
|
* driver, and some must be used by the end user to control the drivers. For
|
|
* example, you must use the Parameter common library in order to set the
|
|
* parameters in the WUDEV module.
|
|
*
|
|
* The common libraries consist of the following:
|
|
*
|
|
* - Connection Contexts - Used internally and can be used by end-user. See dwc_cc.h
|
|
* - Parameters - Used internally and can be used by end-user. See dwc_params.h
|
|
* - Notifications - Used internally and can be used by end-user. See dwc_notifier.h
|
|
* - Lists - Used internally and can be used by end-user. See dwc_list.h
|
|
* - Memory Debugging - Used internally and can be used by end-user. See dwc_os.h
|
|
* - Modpow - Used internally only. See dwc_modpow.h
|
|
* - DH - Used internally only. See dwc_dh.h
|
|
* - Crypto - Used internally only. See dwc_crypto.h
|
|
*
|
|
*
|
|
* @section prereq Prerequistes For dwc_os.h
|
|
* @subsection types Data Types
|
|
*
|
|
* The dwc_os.h file assumes that several low-level data types are pre defined for the
|
|
* compilation environment. These data types are:
|
|
*
|
|
* - uint8_t - unsigned 8-bit data type
|
|
* - int8_t - signed 8-bit data type
|
|
* - uint16_t - unsigned 16-bit data type
|
|
* - int16_t - signed 16-bit data type
|
|
* - uint32_t - unsigned 32-bit data type
|
|
* - int32_t - signed 32-bit data type
|
|
* - uint64_t - unsigned 64-bit data type
|
|
* - int64_t - signed 64-bit data type
|
|
*
|
|
* Ensure that these are defined before using dwc_os.h. The easiest way to do
|
|
* that is to modify the top of the file to include the appropriate header.
|
|
* This is already done for the Linux environment. If the DWC_LINUX macro is
|
|
* defined, the correct header will be added. A standard header <stdint.h> is
|
|
* also used for environments where standard C headers are available.
|
|
*
|
|
* @subsection stdarg Variable Arguments
|
|
*
|
|
* Variable arguments are provided by a standard C header <stdarg.h>. it is
|
|
* available in Both the Linux and ANSI C enviornment. An equivalent must be
|
|
* provided in your enviornment in order to use dwc_os.h with the debug and
|
|
* tracing message functionality.
|
|
*
|
|
* @subsection thread Threading
|
|
*
|
|
* WUDEV Core must be run on an operating system that provides for multiple
|
|
* threads/processes. Threading can be implemented in many ways, even in
|
|
* embedded systems without an operating system. At the bare minimum, the
|
|
* system should be able to start any number of processes at any time to handle
|
|
* special work. It need not be a pre-emptive system. Process context can
|
|
* change upon a call to a blocking function. The hardware interrupt context
|
|
* that calls the module's ISR() function must be differentiable from process
|
|
* context, even if your processes are impemented via a hardware interrupt.
|
|
* Further locking mechanism between process must exist (or be implemented), and
|
|
* process context must have a way to disable interrupts for a period of time to
|
|
* lock them out. If all of this exists, the functions in dwc_os.h related to
|
|
* threading should be able to be implemented with the defined behavior.
|
|
*
|
|
*/
|
|
|
|
#ifdef __cplusplus
|
|
}
|
|
#endif
|
|
|
|
#endif /* _DWC_OS_H_ */
|