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a0f1cc18f9
Add skip list for metrics known would fail because some of the metrics are very likely to fail due to multiplexing or other errors. So add all of the flaky tests into the skip list. Signed-off-by: Weilin Wang <weilin.wang@intel.com> Tested-by: Namhyung Kim <namhyung@kernel.org> Cc: ravi.bangoria@amd.com Cc: Ian Rogers <irogers@google.com> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Adrian Hunter <adrian.hunter@intel.com> Cc: Caleb Biggers <caleb.biggers@intel.com> Cc: Perry Taylor <perry.taylor@intel.com> Cc: Samantha Alt <samantha.alt@intel.com> Cc: Arnaldo Carvalho de Melo <acme@kernel.org> Cc: Jiri Olsa <jolsa@kernel.org> Cc: Kan Liang <kan.liang@linux.intel.com> Cc: Ingo Molnar <mingo@redhat.com> Link: https://lore.kernel.org/r/20230620170027.1861012-3-weilin.wang@intel.com Signed-off-by: Namhyung Kim <namhyung@kernel.org>
398 lines
12 KiB
JSON
398 lines
12 KiB
JSON
{
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"SkipList": [
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"tsx_aborted_cycles",
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"tsx_transactional_cycles",
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"C2_Pkg_Residency",
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"C6_Pkg_Residency",
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"C1_Core_Residency",
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"C6_Core_Residency",
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"tma_false_sharing",
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"tma_remote_cache",
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"tma_contested_accesses"
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],
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"RelationshipRules": [
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{
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"RuleIndex": 1,
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"Formula": "a+b",
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"TestType": "RelationshipTest",
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"RangeLower": "c",
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"RangeUpper": "c",
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"ErrorThreshold": 5.0,
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"Description": "Intel(R) Optane(TM) Persistent Memory(PMEM) bandwidth total includes Intel(R) Optane(TM) Persistent Memory(PMEM) read bandwidth and Intel(R) Optane(TM) Persistent Memory(PMEM) write bandwidth",
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"Metrics": [
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{
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"Name": "pmem_memory_bandwidth_read",
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"Alias": "a"
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},
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{
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"Name": "pmem_memory_bandwidth_write",
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"Alias": "b"
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},
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{
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"Name": "pmem_memory_bandwidth_total",
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"Alias": "c"
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}
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]
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},
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{
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"RuleIndex": 2,
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"Formula": "a+b",
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"TestType": "RelationshipTest",
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"RangeLower": "c",
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"RangeUpper": "c",
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"ErrorThreshold": 5.0,
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"Description": "DDR memory bandwidth total includes DDR memory read bandwidth and DDR memory write bandwidth",
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"Metrics": [
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{
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"Name": "memory_bandwidth_read",
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"Alias": "a"
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},
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{
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"Name": "memory_bandwidth_write",
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"Alias": "b"
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},
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{
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"Name": "memory_bandwidth_total",
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"Alias": "c"
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}
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]
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},
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{
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"RuleIndex": 3,
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"Formula": "a+b",
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"TestType": "RelationshipTest",
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"RangeLower": "100",
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"RangeUpper": "100",
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"ErrorThreshold": 5.0,
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"Description": "Total memory read accesses includes memory reads from last level cache (LLC) addressed to local DRAM and memory reads from the last level cache (LLC) addressed to remote DRAM.",
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"Metrics": [
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{
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"Name": "numa_reads_addressed_to_local_dram",
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"Alias": "a"
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},
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{
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"Name": "numa_reads_addressed_to_remote_dram",
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"Alias": "b"
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}
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]
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},
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{
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"RuleIndex": 4,
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"Formula": "a",
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"TestType": "SingleMetricTest",
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"RangeLower": "0.125",
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"RangeUpper": "",
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"ErrorThreshold": "",
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"Description": "",
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"Metrics": [
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{
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"Name": "cpi",
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"Alias": "a"
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}
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]
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},
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{
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"RuleIndex": 5,
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"Formula": "",
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"TestType": "SingleMetricTest",
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"RangeLower": "0",
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"RangeUpper": "1",
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"ErrorThreshold": 5.0,
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"Description": "Ratio values should be within value range [0,1)",
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"Metrics": [
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{
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"Name": "loads_per_instr",
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"Alias": ""
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},
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{
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"Name": "stores_per_instr",
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"Alias": ""
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},
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{
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"Name": "l1d_mpi",
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"Alias": ""
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},
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{
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"Name": "l1d_demand_data_read_hits_per_instr",
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"Alias": ""
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},
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{
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"Name": "l1_i_code_read_misses_with_prefetches_per_instr",
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"Alias": ""
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},
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{
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"Name": "l2_demand_data_read_hits_per_instr",
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"Alias": ""
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},
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{
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"Name": "l2_mpi",
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"Alias": ""
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},
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{
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"Name": "l2_demand_data_read_mpi",
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"Alias": ""
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},
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{
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"Name": "l2_demand_code_mpi",
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"Alias": ""
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}
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]
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},
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{
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"RuleIndex": 6,
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"Formula": "a+b+c+d",
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"TestType": "RelationshipTest",
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"RangeLower": "100",
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"RangeUpper": "100",
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"ErrorThreshold": 5.0,
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"Description": "Sum of TMA level 1 metrics should be 100%",
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"Metrics": [
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{
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"Name": "tma_frontend_bound",
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"Alias": "a"
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},
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{
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"Name": "tma_bad_speculation",
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"Alias": "b"
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},
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{
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"Name": "tma_backend_bound",
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"Alias": "c"
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},
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{
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"Name": "tma_retiring",
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"Alias": "d"
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}
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]
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},
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{
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"RuleIndex": 7,
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"Formula": "a+b",
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"TestType": "RelationshipTest",
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"RangeLower": "c",
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"RangeUpper": "c",
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"ErrorThreshold": 5.0,
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"Description": "Sum of the level 2 children should equal level 1 parent",
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"Metrics": [
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{
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"Name": "tma_fetch_latency",
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"Alias": "a"
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},
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{
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"Name": "tma_fetch_bandwidth",
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"Alias": "b"
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},
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{
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"Name": "tma_frontend_bound",
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"Alias": "c"
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}
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]
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},
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{
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"RuleIndex": 8,
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"Formula": "a+b",
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"TestType": "RelationshipTest",
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"RangeLower": "c",
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"RangeUpper": "c",
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"ErrorThreshold": 5.0,
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"Description": "Sum of the level 2 children should equal level 1 parent",
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"Metrics": [
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{
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"Name": "tma_branch_mispredicts",
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"Alias": "a"
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},
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{
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"Name": "tma_machine_clears",
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"Alias": "b"
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},
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{
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"Name": "tma_bad_speculation",
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"Alias": "c"
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}
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]
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},
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{
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"RuleIndex": 9,
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"Formula": "a+b",
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"TestType": "RelationshipTest",
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"RangeLower": "c",
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"RangeUpper": "c",
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"ErrorThreshold": 5.0,
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"Description": "Sum of the level 2 children should equal level 1 parent",
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"Metrics": [
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{
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"Name": "tma_memory_bound",
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"Alias": "a"
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},
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{
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"Name": "tma_core_bound",
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"Alias": "b"
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},
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{
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"Name": "tma_backend_bound",
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"Alias": "c"
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}
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]
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},
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{
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"RuleIndex": 10,
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"Formula": "a+b",
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"TestType": "RelationshipTest",
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"RangeLower": "c",
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"RangeUpper": "c",
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"ErrorThreshold": 5.0,
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"Description": "Sum of the level 2 children should equal level 1 parent",
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"Metrics": [
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{
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"Name": "tma_light_operations",
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"Alias": "a"
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},
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{
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"Name": "tma_heavy_operations",
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"Alias": "b"
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},
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{
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"Name": "tma_retiring",
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"Alias": "c"
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}
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]
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},
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{
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"RuleIndex": 11,
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"Formula": "a+b+c",
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"TestType": "RelationshipTest",
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"RangeLower": "100",
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"RangeUpper": "100",
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"ErrorThreshold": 5.0,
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"Description": "The all_requests includes the memory_page_empty, memory_page_misses, and memory_page_hits equals.",
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"Metrics": [
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{
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"Name": "memory_page_empty_vs_all_requests",
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"Alias": "a"
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},
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{
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"Name": "memory_page_misses_vs_all_requests",
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"Alias": "b"
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},
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{
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"Name": "memory_page_hits_vs_all_requests",
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"Alias": "c"
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}
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]
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},
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{
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"RuleIndex": 12,
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"Formula": "a-b",
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"TestType": "RelationshipTest",
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"RangeLower": "0",
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"RangeUpper": "",
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"ErrorThreshold": 5.0,
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"Description": "CPU utilization in kernel mode should always be <= cpu utilization",
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"Metrics": [
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{
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"Name": "cpu_utilization",
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"Alias": "a"
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},
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{
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"Name": "cpu_utilization_in_kernel_mode",
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"Alias": "b"
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}
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]
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},
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{
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"RuleIndex": 13,
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"Formula": "a-b",
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"TestType": "RelationshipTest",
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"RangeLower": "0",
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"RangeUpper": "",
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"ErrorThreshold": 5.0,
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"Description": "Total L2 misses per instruction should be >= L2 demand data read misses per instruction",
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"Metrics": [
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{
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"Name": "l2_mpi",
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"Alias": "a"
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},
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{
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"Name": "l2_demand_data_read_mpi",
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"Alias": "b"
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}
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]
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},
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{
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"RuleIndex": 14,
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"Formula": "a-b",
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"TestType": "RelationshipTest",
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"RangeLower": "0",
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"RangeUpper": "",
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"ErrorThreshold": 5.0,
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"Description": "Total L2 misses per instruction should be >= L2 demand code misses per instruction",
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"Metrics": [
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{
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"Name": "l2_mpi",
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"Alias": "a"
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},
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{
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"Name": "l2_demand_code_mpi",
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"Alias": "b"
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}
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]
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},
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{
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"RuleIndex": 15,
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"Formula": "b+c+d",
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"TestType": "RelationshipTest",
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"RangeLower": "a",
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"RangeUpper": "a",
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"ErrorThreshold": 5.0,
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"Description": "L3 data read, rfo, code misses per instruction equals total L3 misses per instruction.",
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"Metrics": [
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{
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"Name": "llc_mpi",
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"Alias": "a"
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},
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{
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"Name": "llc_data_read_mpi_demand_plus_prefetch",
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"Alias": "b"
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},
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{
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"Name": "llc_rfo_read_mpi_demand_plus_prefetch",
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"Alias": "c"
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},
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{
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"Name": "llc_code_read_mpi_demand_plus_prefetch",
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"Alias": "d"
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}
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]
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},
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{
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"RuleIndex": 16,
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"Formula": "a",
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"TestType": "SingleMetricTest",
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"RangeLower": "0",
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"RangeUpper": "8",
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"ErrorThreshold": 0.0,
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"Description": "Setting generous range for allowable frequencies",
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"Metrics": [
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{
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"Name": "uncore_freq",
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"Alias": "a"
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}
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]
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},
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{
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"RuleIndex": 17,
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"Formula": "a",
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"TestType": "SingleMetricTest",
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"RangeLower": "0",
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"RangeUpper": "8",
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"ErrorThreshold": 0.0,
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"Description": "Setting generous range for allowable frequencies",
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"Metrics": [
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{
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"Name": "cpu_operating_frequency",
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"Alias": "a"
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}
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]
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}
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]
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} |