Codrin Ciubotariu fd165f9763 clk: at91: clk-generated: Limit the requested rate to our range ...

[ Upstream commit af7651e67b ]

On clk_generated_determine_rate(), the requested rate could be outside
of clk's range. Limit the rate to the clock's range to not return an
error.

Fixes: df70aeef60 ("clk: at91: add generated clock driver")
Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@microchip.com>
Link: https://lore.kernel.org/r/20210707131213.3283509-1-codrin.ciubotariu@microchip.com
Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>

2021-09-18 13:43:33 +02:00

..

at91rm9200.c

clk: at91: Fix the declaration of the clocks

2021-02-09 16:54:44 -08:00

at91sam9g45.c

clk: at91: Fix the declaration of the clocks

2021-02-09 16:54:44 -08:00

at91sam9n12.c

clk: at91: Fix the declaration of the clocks

2021-02-09 16:54:44 -08:00

at91sam9rl.c

clk: at91: Fix the declaration of the clocks

2021-02-09 16:54:44 -08:00

at91sam9x5.c

clk: at91: Fix the declaration of the clocks

2021-02-09 16:54:44 -08:00

at91sam9260.c

clk: at91: Fix the declaration of the clocks

2021-02-09 16:54:44 -08:00

clk-audio-pll.c

treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 152

2019-05-30 11:26:32 -07:00

clk-generated.c

clk: at91: clk-generated: Limit the requested rate to our range

2021-09-18 13:43:33 +02:00

clk-h32mx.c

treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 152

2019-05-30 11:26:32 -07:00

clk-i2s-mux.c

clk: at91: move DT compatibility code to its own file

2018-10-17 10:45:39 -07:00

clk-main.c

clk: at91: clk-main: update key before writing AT91_CKGR_MOR

2020-10-13 19:59:01 -07:00

clk-master.c

clk: at91: clk-master: re-factor master clock

2020-12-19 11:50:56 -08:00

clk-peripheral.c

clk: at91: remove the checking of parent_name

2020-10-13 19:59:01 -07:00

clk-pll.c

treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 152

2019-05-30 11:26:32 -07:00

clk-plldiv.c

treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 152

2019-05-30 11:26:32 -07:00

clk-programmable.c

clk: at91: clk-programmable: add mux_table option

2020-07-24 02:19:08 -07:00

clk-sam9x60-pll.c

clk: at91: clk-sam9x60-pll: allow runtime changes for pll

2020-12-19 11:50:55 -08:00

clk-slow.c

treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 152

2019-05-30 11:26:32 -07:00

clk-smd.c

treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 152

2019-05-30 11:26:32 -07:00

clk-system.c

clk: at91: replace conditional operator with double logical not

2020-07-24 02:19:08 -07:00

clk-usb.c

clk: at91: usb: introduce num_parents in driver's structure

2020-02-12 15:31:47 -08:00

clk-utmi.c

clk: at91: clk-utmi: add utmi support for sama7g5

2020-07-24 02:19:08 -07:00

dt-compat.c

clk: at91: clk-master: re-factor master clock

2020-12-19 11:50:56 -08:00

Makefile

clk: at91: sama7g5: add clock support for sama7g5

2020-07-24 02:19:09 -07:00

pmc.c

clk: at91: allow setting PCKx parent via DT

2020-05-26 20:22:43 -07:00

pmc.h

clk: at91: clk-master: re-factor master clock

2020-12-19 11:50:56 -08:00

sam9x60.c

clk: at91: sam9x60: remove atmel,osc-bypass support

2020-12-19 15:33:00 -08:00

sama5d2.c

clk: at91: Fix the declaration of the clocks

2021-02-09 16:54:44 -08:00

sama5d3.c

clk: at91: Fix the declaration of the clocks

2021-02-09 16:54:44 -08:00

sama5d4.c

clk: at91: Fix the declaration of the clocks

2021-02-09 16:54:44 -08:00

sama7g5.c

clk: at91: Trivial typo fixes in the file sama7g5.c

2021-03-13 13:02:02 -08:00

sckc.c

clk: at91: sckc: register slow_rc with accuracy option

2020-07-24 02:19:08 -07:00