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5e940312a2
Boot Survivability is a software based workflow for recovering a system
in a failed boot state. Here system recoverability is concerned with
recovering the firmware responsible for boot.
This is implemented by loading the driver with bare minimum (no drm card)
to allow the firmware to be flashed through mei-gsc and collect telemetry.
The driver's probe flow is modified such that it enters survivability mode
when pcode initialization is incomplete and boot status denotes a failure.
In this mode, drm card is not exposed and presence of survivability_mode
entry in PCI sysfs is used to indicate survivability mode and
provide additional information required for debug
This patch adds initialization functions and exposes admin
readable sysfs entries
The new sysfs will have the below layout
/sys/bus/.../bdf
├── survivability_mode
v2: reorder headers
fix doc
remove survivability info and use mode to display information
use separate function for logging survivability information
for critical error (Rodrigo)
v3: use for loop
use dev logs instead of drm
use helper function for aux history(Rodrigo)
remove unnecessary error check of greater than max_scratch
as we are reading only 3 bit
v4: fix checkpatch warnings
fix space (Rodrigo)
rename register
Signed-off-by: Riana Tauro <riana.tauro@intel.com>
Acked-by: Ashwin Kumar Kulkarni <ashwin.kumar.kulkarni@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20250128095632.1294722-2-riana.tauro@intel.com
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
71 lines
2.1 KiB
C
71 lines
2.1 KiB
C
/* SPDX-License-Identifier: MIT */
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/*
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* Copyright © 2022 Intel Corporation
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*/
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/* Internal to xe_pcode */
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#include "regs/xe_reg_defs.h"
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#define PCODE_MAILBOX XE_REG(0x138124)
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#define PCODE_READY REG_BIT(31)
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#define PCODE_MB_PARAM2 REG_GENMASK(23, 16)
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#define PCODE_MB_PARAM1 REG_GENMASK(15, 8)
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#define PCODE_MB_COMMAND REG_GENMASK(7, 0)
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#define PCODE_ERROR_MASK 0xFF
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#define PCODE_SUCCESS 0x0
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#define PCODE_ILLEGAL_CMD 0x1
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#define PCODE_TIMEOUT 0x2
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#define PCODE_ILLEGAL_DATA 0x3
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#define PCODE_ILLEGAL_SUBCOMMAND 0x4
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#define PCODE_LOCKED 0x6
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#define PCODE_GT_RATIO_OUT_OF_RANGE 0x10
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#define PCODE_REJECTED 0x11
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#define PCODE_DATA0 XE_REG(0x138128)
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#define PCODE_DATA1 XE_REG(0x13812C)
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/* Min Freq QOS Table */
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#define PCODE_WRITE_MIN_FREQ_TABLE 0x8
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#define PCODE_READ_MIN_FREQ_TABLE 0x9
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#define PCODE_FREQ_RING_RATIO_SHIFT 16
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/* PCODE Init */
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#define DGFX_PCODE_STATUS 0x7E
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#define DGFX_GET_INIT_STATUS 0x0
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#define DGFX_INIT_STATUS_COMPLETE 0x1
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#define PCODE_POWER_SETUP 0x7C
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#define POWER_SETUP_SUBCOMMAND_READ_I1 0x4
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#define POWER_SETUP_SUBCOMMAND_WRITE_I1 0x5
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#define POWER_SETUP_I1_WATTS REG_BIT(31)
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#define POWER_SETUP_I1_SHIFT 6 /* 10.6 fixed point format */
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#define POWER_SETUP_I1_DATA_MASK REG_GENMASK(15, 0)
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#define PCODE_FREQUENCY_CONFIG 0x6e
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/* Frequency Config Sub Commands (param1) */
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#define PCODE_MBOX_FC_SC_READ_FUSED_P0 0x0
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#define PCODE_MBOX_FC_SC_READ_FUSED_PN 0x1
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/* Domain IDs (param2) */
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#define PCODE_MBOX_DOMAIN_HBM 0x2
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#define PCODE_SCRATCH(x) XE_REG(0x138320 + ((x) * 4))
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/* PCODE_SCRATCH0 */
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#define AUXINFO_REG_OFFSET REG_GENMASK(17, 15)
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#define OVERFLOW_REG_OFFSET REG_GENMASK(14, 12)
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#define HISTORY_TRACKING REG_BIT(11)
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#define OVERFLOW_SUPPORT REG_BIT(10)
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#define AUXINFO_SUPPORT REG_BIT(9)
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#define BOOT_STATUS REG_GENMASK(3, 1)
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#define CRITICAL_FAILURE 4
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#define NON_CRITICAL_FAILURE 7
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/* Auxiliary info bits */
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#define AUXINFO_HISTORY_OFFSET REG_GENMASK(31, 29)
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struct pcode_err_decode {
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int errno;
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const char *str;
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};
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