Files
linux/drivers/gpu/drm/amd/amdgpu
Hawking Zhang 554bdbf6de drm/amdgpu: use cached ih rb control reg offsets for vega10
all the ih rb control register offsets are cached
at the beginning of ih_sw_init.

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Acked-by: Felix Kuehling <Felix.Kuehling@amd.com>
Reviewed-by: Dennis Li <Dennis.Li@amd.com>
Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-12-23 15:04:14 -05:00
..
2020-11-24 12:06:10 -05:00
2019-06-10 23:00:01 +02:00
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2020-07-01 01:59:24 -04:00
2020-07-02 12:02:50 -04:00