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MISR support is the debug feature present in Snapdragon chipsets. At the layer mixer and interfaces, MISR algorithm can generate CRC signatures of the pixel data which can be used for validating the frames generated. Since there are no clients for this feature, strip down the support from the driver. changes in v4: - changed introduced in the series changes in v5: - update commit text with the need for the change(Sean) Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org> Signed-off-by: Sean Paul <seanpaul@chromium.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
116 lines
2.9 KiB
C
116 lines
2.9 KiB
C
/* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef _DPU_HW_LM_H
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#define _DPU_HW_LM_H
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#include "dpu_hw_mdss.h"
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#include "dpu_hw_util.h"
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#include "dpu_hw_blk.h"
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struct dpu_hw_mixer;
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struct dpu_hw_mixer_cfg {
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u32 out_width;
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u32 out_height;
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bool right_mixer;
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int flags;
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};
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struct dpu_hw_color3_cfg {
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u8 keep_fg[DPU_STAGE_MAX];
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};
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/**
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*
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* struct dpu_hw_lm_ops : Interface to the mixer Hw driver functions
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* Assumption is these functions will be called after clocks are enabled
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*/
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struct dpu_hw_lm_ops {
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/*
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* Sets up mixer output width and height
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* and border color if enabled
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*/
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void (*setup_mixer_out)(struct dpu_hw_mixer *ctx,
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struct dpu_hw_mixer_cfg *cfg);
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/*
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* Alpha blending configuration
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* for the specified stage
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*/
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void (*setup_blend_config)(struct dpu_hw_mixer *ctx, uint32_t stage,
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uint32_t fg_alpha, uint32_t bg_alpha, uint32_t blend_op);
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/*
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* Alpha color component selection from either fg or bg
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*/
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void (*setup_alpha_out)(struct dpu_hw_mixer *ctx, uint32_t mixer_op);
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/**
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* setup_border_color : enable/disable border color
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*/
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void (*setup_border_color)(struct dpu_hw_mixer *ctx,
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struct dpu_mdss_color *color,
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u8 border_en);
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/**
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* setup_gc : enable/disable gamma correction feature
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*/
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void (*setup_gc)(struct dpu_hw_mixer *mixer,
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void *cfg);
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};
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struct dpu_hw_mixer {
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struct dpu_hw_blk base;
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struct dpu_hw_blk_reg_map hw;
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/* lm */
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enum dpu_lm idx;
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const struct dpu_lm_cfg *cap;
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const struct dpu_mdp_cfg *mdp;
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const struct dpu_ctl_cfg *ctl;
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/* ops */
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struct dpu_hw_lm_ops ops;
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/* store mixer info specific to display */
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struct dpu_hw_mixer_cfg cfg;
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};
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/**
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* to_dpu_hw_mixer - convert base object dpu_hw_base to container
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* @hw: Pointer to base hardware block
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* return: Pointer to hardware block container
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*/
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static inline struct dpu_hw_mixer *to_dpu_hw_mixer(struct dpu_hw_blk *hw)
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{
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return container_of(hw, struct dpu_hw_mixer, base);
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}
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/**
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* dpu_hw_lm_init(): Initializes the mixer hw driver object.
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* should be called once before accessing every mixer.
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* @idx: mixer index for which driver object is required
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* @addr: mapped register io address of MDP
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* @m : pointer to mdss catalog data
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*/
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struct dpu_hw_mixer *dpu_hw_lm_init(enum dpu_lm idx,
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void __iomem *addr,
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struct dpu_mdss_cfg *m);
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/**
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* dpu_hw_lm_destroy(): Destroys layer mixer driver context
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* @lm: Pointer to LM driver context
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*/
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void dpu_hw_lm_destroy(struct dpu_hw_mixer *lm);
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#endif /*_DPU_HW_LM_H */
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