Thierry Reding 3950be0f2d drm/tegra: dpaux: Fix transfers larger than 4 bytes ...

commit 3c1dae0a07 upstream.

The DPAUX read/write FIFO registers aren't sequential in the register
space, causing transfers larger than 4 bytes to cause accesses to non-
existing FIFO registers.

Fixes: 6b6b604215 ("drm/tegra: Add eDP support")
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

2015-08-03 09:29:08 -07:00

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