Alvin Lee 75a3371e8f drm/amd/display: Increase num voltage states to 40 ...

[Description]
If during driver init stage there are greater than 20
intermediary voltage states while constructing the SOC
BB we could hit issues because we will index outside of the
clock_limits array and start overwriting data. Increase the
total number of states to 40 to avoid this issue.

Cc: stable@vger.kernel.org # 6.1+
Reviewed-by: Samson Tam <samson.tam@amd.com>
Acked-by: Hamza Mahfooz <hamza.mahfooz@amd.com>
Signed-off-by: Alvin Lee <alvin.lee2@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

2023-11-29 16:48:59 -05:00

..

amdgpu_dm

drm/amd/display: Remove redundant DRM device struct in amdgpu_dm_, mst_types.c

2023-11-29 16:23:39 -05:00

dc

drm/amd/display: Increase num voltage states to 40

2023-11-29 16:48:59 -05:00

dmub

drm/amd/display: replay: generalize the send command function usage

2023-11-29 16:48:59 -05:00

include

drm/amd/display: Add missing chips for HDCP

2023-11-17 09:30:50 -05:00

modules

drm/amd/display: Send PQ bit in AMD VSIF

2023-11-17 09:30:50 -05:00

Kconfig

drm/amd/display: Allow building DC with clang on RISC-V

2023-07-21 16:52:25 -04:00

Makefile

drm/amd/display: Refactor DSC into component folder

2023-11-29 16:48:59 -05:00

TODO

…