Alvin Lee f0ec30549a drm/amd/display: Ensure populate uclk in bb construction ...

[Description]
- For some SKUs, the optimal DCFCLK for each UCLK is less than the
  smallest DCFCLK STA target due to low memory bandwidth. There is
  an assumption that the DCFCLK STA targets will always be less
  than one of the optimal DCFCLK values, but this is not true for
  SKUs that have low memory bandwidth. In this case we need to
  populate the optimal UCLK for each DCFCLK STA targets as the max
  UCLK freq.
- Also fix a bug in DML where start_state is not assigned and used
  correctly.

Reviewed-by: Samson Tam <samson.tam@amd.com>
Reviewed-by: Chaitanya Dhere <chaitanya.dhere@amd.com>
Acked-by: Alex Hung <alex.hung@amd.com>
Signed-off-by: Alvin Lee <alvin.lee2@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

2024-01-15 18:35:39 -05:00

..

dcn303_fpu.c

drm/amd/display: Ensure populate uclk in bb construction

2024-01-15 18:35:39 -05:00

dcn303_fpu.h

drm/amd/display: move FPU associated DCN303 code to DML folder

2022-03-15 14:25:15 -04:00