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8c8b997c34
Add Exegin Q5xR5. The base device tree is from OpenWrt tree and with
the addition of this patch there will be no need to maintain it
separatelly in OpenWrt.
[osk: original author of patch in OpenWrt]
[claudiu.beznea: use "&<label> {" syntax, sorted nodes in alphabetical
order, adapted flash to new support in kernel 5.14, use proper
compatibles according to kernel 5.14, use macros instead of
hardcoded numbers for pinctrl phandles and for all pinctrl references,
add pinctrl-names, pinctrl-X where necessaray]
Signed-off-by: Owen Kirby <osk@exegin.com>
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Link: https://lore.kernel.org/r/20210816064416.1630674-8-claudiu.beznea@microchip.com
200 lines
3.4 KiB
Plaintext
200 lines
3.4 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Device Tree file for Exegin Q5xR5 board
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*
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* Copyright (C) 2014 Owen Kirby <osk@exegin.com>
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*/
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/dts-v1/;
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#include "at91sam9g20.dtsi"
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/ {
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model = "Exegin Q5x (rev5)";
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compatible = "exegin,q5xr5", "atmel,at91sam9g20", "atmel,at91sam9";
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chosen {
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bootargs = "console=ttyS0,115200 rootfstype=squashfs,jffs2";
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};
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memory {
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reg = <0x20000000 0x0>;
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};
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clocks {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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main_clock: clock@0 {
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compatible = "atmel,osc", "fixed-clock";
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clock-frequency = <18432000>;
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};
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slow_xtal {
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clock-frequency = <32768>;
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};
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main_xtal {
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clock-frequency = <18432000>;
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};
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};
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};
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&dbgu {
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status = "okay";
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};
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&ebi {
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status = "okay";
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flash: flash@0 {
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compatible = "cfi-flash";
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0x0 0x1000000 0x800000>;
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bank-width = <2>;
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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kernel@0 {
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label = "kernel";
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reg = <0x0 0x200000>;
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};
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rootfs@200000 {
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label = "rootfs";
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reg = <0x200000 0x600000>;
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};
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};
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};
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};
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&macb0 {
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phy-mode = "mii";
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status = "okay";
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};
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&pinctrl {
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board {
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pinctrl_pck0_as_mck: pck0_as_mck {
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atmel,pins = <AT91_PIOC 1 AT91_PERIPH_B AT91_PINCTRL_NONE>;
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};
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};
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spi0 {
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pinctrl_spi0: spi0-0 {
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atmel,pins =
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<AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE
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AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE
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AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE>;
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};
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pinctrl_spi0_npcs0: spi0_npcs0 {
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atmel,pins = <AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE>;
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};
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pinctrl_spi0_npcs1: spi0_npcs1 {
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atmel,pins = <AT91_PIOC 11 AT91_PERIPH_B AT91_PINCTRL_NONE>;
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};
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};
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spi1 {
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pinctrl_spi1: spi1-0 {
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atmel,pins =
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<AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE
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AT91_PIOB 1 AT91_PERIPH_A AT91_PINCTRL_NONE
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AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE>;
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};
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pinctrl_spi1_npcs0: spi1_npcs0 {
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atmel,pins = <AT91_PIOB 3 AT91_PERIPH_A AT91_PINCTRL_NONE>;
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};
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pinctrl_spi1_npcs1: spi1_npcs1 {
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atmel,pins = <AT91_PIOC 5 AT91_PERIPH_B AT91_PINCTRL_NONE>;
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};
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};
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};
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&spi0 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_spi0 &pinctrl_spi0_npcs0 &pinctrl_spi0_npcs1>;
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cs-gpios = <&pioA 3 GPIO_ACTIVE_HIGH>, <&pioC 11 GPIO_ACTIVE_LOW>, <0>, <0>;
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status = "okay";
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m25p80@0 {
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compatible = "jedec,spi-nor";
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spi-max-frequency = <20000000>;
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reg = <0>;
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#address-cells = <1>;
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#size-cells = <1>;
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at91boot@0 {
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label = "at91boot";
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reg = <0x0 0x4000>;
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};
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uenv@4000 {
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label = "uboot-env";
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reg = <0x4000 0x4000>;
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};
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uboot@8000 {
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label = "uboot";
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reg = <0x8000 0x3E000>;
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};
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};
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spidev@1 {
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compatible = "spidev";
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spi-max-frequency = <2000000>;
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reg = <1>;
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};
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};
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&spi1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_spi1 &pinctrl_spi1_npcs0 &pinctrl_spi1_npcs1>;
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cs-gpios = <&pioB 3 GPIO_ACTIVE_HIGH>, <&pioC 5 GPIO_ACTIVE_LOW>, <0>, <0>;
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status = "okay";
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spidev@0 {
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compatible = "spidev";
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spi-max-frequency = <2000000>;
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reg = <0>;
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};
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spidev@1 {
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compatible = "spidev";
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spi-max-frequency = <2000000>;
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reg = <1>;
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};
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};
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&usart0 {
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pinctrl-0 =
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<&pinctrl_usart0
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&pinctrl_usart0_rts
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&pinctrl_usart0_cts
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&pinctrl_usart0_dtr_dsr
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&pinctrl_usart0_dcd
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&pinctrl_usart0_ri>;
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status = "okay";
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};
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&usb0 {
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num-ports = <2>;
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status = "okay";
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};
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&usb1 {
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status = "okay";
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};
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&watchdog {
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status = "okay";
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};
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