Files
linux/drivers/gpu/drm
Victor Lu 8b22f04833 drm/amdgpu: clear RB_OVERFLOW bit when enabling interrupts for vega20_ih
Port this change to vega20_ih.c:
commit afbf7955ff ("drm/amdgpu: clear RB_OVERFLOW bit when enabling interrupts")

Original commit message:
"Why:
Setting IH_RB_WPTR register to 0 will not clear the RB_OVERFLOW bit
if RB_ENABLE is not set.

How to fix:
Set WPTR_OVERFLOW_CLEAR bit after RB_ENABLE bit is set.
The RB_ENABLE bit is required to be set, together with
WPTR_OVERFLOW_ENABLE bit so that setting WPTR_OVERFLOW_CLEAR bit
would clear the RB_OVERFLOW."

Signed-off-by: Victor Lu <victorchengchi.lu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-10-22 17:50:40 -04:00
..
2024-08-22 09:13:21 +02:00
2024-09-11 09:18:15 +02:00
2024-08-28 12:21:49 -03:00
2024-09-11 09:18:15 +02:00
2024-09-11 09:18:15 +02:00
2024-09-11 09:18:15 +02:00
2024-09-11 09:18:15 +02:00
2024-08-09 08:13:48 +02:00
2024-09-11 09:18:15 +02:00
2024-09-11 09:18:15 +02:00
2024-09-11 09:18:15 +02:00
2024-09-11 09:18:15 +02:00
2024-09-11 09:18:15 +02:00
2024-09-11 09:18:15 +02:00
2024-09-11 09:18:15 +02:00
2024-09-11 09:18:15 +02:00
2024-08-27 14:09:45 +02:00
2024-09-11 09:18:15 +02:00
2024-08-15 11:01:48 -03:00
2024-06-24 17:08:53 +03:00
2024-08-23 16:55:35 +02:00
2024-09-11 09:18:15 +02:00