Meenakshikumar Somasundaram 8aaeb25327 drm/amd/display: Fix pixel rate divider policy for 1 pixel per cycle config ...

[Why]
Pixel rate dividor was not programmed correctly for 1 pixel per cycle
configuration for empty tu case.

[How]
Included check for empty tu when pixel rate dividor values were selected.

Reviewed-by: Michael Strauss <michael.strauss@amd.com>
Signed-off-by: Meenakshikumar Somasundaram <meenakshikumar.somasundaram@amd.com>
Signed-off-by: Zaeem Mohamed <zaeem.mohamed@amd.com>
Tested-by: Mark Broadworth <mark.broadworth@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

2025-04-22 08:51:44 -04:00

..

dcn32_hwseq.c

drm/amd/display: Fix pixel rate divider policy for 1 pixel per cycle config

2025-04-22 08:51:44 -04:00

dcn32_hwseq.h

drm/amd/display: Unify blank_phantom and blank_pixel_data

2024-10-07 14:10:21 -04:00

dcn32_init.c

drm/amd/display: Add clear DCC and Tiling callback for DCN

2025-02-19 15:13:20 -05:00

dcn32_init.h

drm/amd/display: Refactor INIT into component folder

2024-01-03 10:47:29 -05:00