Remington Brasga 3834ce3600 drm/amdgpu/uvd4: fix mask and shift definitions ...

A few define's are listed twice with different, incorrect values.
This fix sets them appropriately.

Signed-off-by: Remington Brasga <rbrasga@uci.edu>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

2024-08-13 10:26:48 -04:00

..

uvd_3_1_d.h

drm amdgpu: SI UVD registers

2020-07-01 01:59:24 -04:00

uvd_3_1_sh_mask.h

drm amdgpu: SI UVD registers

2020-07-01 01:59:24 -04:00

uvd_4_0_d.h

drm/amd/amdgpu: Introduction of SI registers (v2)

2016-11-11 10:21:07 -05:00

uvd_4_0_sh_mask.h

drm/amdgpu/uvd4: fix mask and shift definitions

2024-08-13 10:26:48 -04:00

uvd_4_2_d.h

drm/amdgpu: add support for UVD_NO_OP register

2016-08-24 16:25:04 -04:00

uvd_4_2_sh_mask.h

…

uvd_5_0_d.h

drm/amdgpu: switch UVD code to use UVD_NO_OP for padding

2016-08-24 16:25:05 -04:00

uvd_5_0_enum.h

…

uvd_5_0_sh_mask.h

…

uvd_6_0_d.h

drm/amdgpu: add uvd enc registers in header

2017-10-06 17:43:53 -04:00

uvd_6_0_enum.h

…

uvd_6_0_sh_mask.h

…

uvd_7_0_offset.h

drm/amd/amdgpu: add mmUVD_FW_STATUS register to uvd700

2020-09-17 17:59:54 -04:00

uvd_7_0_sh_mask.h

drm/amd/amdgpu: add mmUVD_FW_STATUS register to uvd700

2020-09-17 17:59:54 -04:00