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ac3a4b17e0
SPI operations have been initially described through macros implicitly implying the use of a single SPI SDR bus. Macros for supporting dual and quad I/O transfers have been added on top, generally inspired by vendor naming, followed by DTR operations. Soon we might see octal and even octal DTR operations as well (including the opcode byte). Let's clarify what the macro really means by describing the expected bus topology in the (quad) program load macro name. While at modifying it, better add the missing_ OP suffix to align with all the other macros of the same kind. Acked-by: Tudor Ambarus <tudor.ambarus@linaro.org> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
106 lines
3.0 KiB
C
106 lines
3.0 KiB
C
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2023, SberDevices. All Rights Reserved.
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*
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* Author: Martin Kurbanov <mmkurbanov@salutedevices.com>
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*/
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#include <linux/device.h>
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#include <linux/kernel.h>
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#include <linux/mtd/spinand.h>
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#define SPINAND_MFR_FORESEE 0xCD
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static SPINAND_OP_VARIANTS(read_cache_variants,
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SPINAND_PAGE_READ_FROM_CACHE_1S_1S_4S_OP(0, 1, NULL, 0),
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SPINAND_PAGE_READ_FROM_CACHE_1S_1S_2S_OP(0, 1, NULL, 0),
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SPINAND_PAGE_READ_FROM_CACHE_FAST_1S_1S_1S_OP(0, 1, NULL, 0),
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SPINAND_PAGE_READ_FROM_CACHE_1S_1S_1S_OP(0, 1, NULL, 0));
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static SPINAND_OP_VARIANTS(write_cache_variants,
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SPINAND_PROG_LOAD_1S_1S_4S_OP(true, 0, NULL, 0),
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SPINAND_PROG_LOAD_1S_1S_1S_OP(true, 0, NULL, 0));
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static SPINAND_OP_VARIANTS(update_cache_variants,
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SPINAND_PROG_LOAD_1S_1S_4S_OP(false, 0, NULL, 0),
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SPINAND_PROG_LOAD_1S_1S_1S_OP(false, 0, NULL, 0));
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static int f35sqa002g_ooblayout_ecc(struct mtd_info *mtd, int section,
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struct mtd_oob_region *region)
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{
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return -ERANGE;
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}
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static int f35sqa002g_ooblayout_free(struct mtd_info *mtd, int section,
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struct mtd_oob_region *region)
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{
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if (section)
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return -ERANGE;
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/* Reserve 2 bytes for the BBM. */
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region->offset = 2;
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region->length = 62;
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return 0;
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}
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static const struct mtd_ooblayout_ops f35sqa002g_ooblayout = {
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.ecc = f35sqa002g_ooblayout_ecc,
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.free = f35sqa002g_ooblayout_free,
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};
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static int f35sqa002g_ecc_get_status(struct spinand_device *spinand, u8 status)
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{
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struct nand_device *nand = spinand_to_nand(spinand);
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switch (status & STATUS_ECC_MASK) {
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case STATUS_ECC_NO_BITFLIPS:
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return 0;
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case STATUS_ECC_HAS_BITFLIPS:
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return nanddev_get_ecc_conf(nand)->strength;
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default:
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break;
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}
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/* More than 1-bit error was detected in one or more sectors and
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* cannot be corrected.
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*/
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return -EBADMSG;
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}
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static const struct spinand_info foresee_spinand_table[] = {
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SPINAND_INFO("F35SQA002G",
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SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x72, 0x72),
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NAND_MEMORG(1, 2048, 64, 64, 2048, 40, 1, 1, 1),
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NAND_ECCREQ(1, 512),
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SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
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&write_cache_variants,
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&update_cache_variants),
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SPINAND_HAS_QE_BIT,
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SPINAND_ECCINFO(&f35sqa002g_ooblayout,
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f35sqa002g_ecc_get_status)),
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SPINAND_INFO("F35SQA001G",
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SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x71, 0x71),
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NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1),
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NAND_ECCREQ(1, 512),
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SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
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&write_cache_variants,
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&update_cache_variants),
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SPINAND_HAS_QE_BIT,
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SPINAND_ECCINFO(&f35sqa002g_ooblayout,
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f35sqa002g_ecc_get_status)),
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};
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static const struct spinand_manufacturer_ops foresee_spinand_manuf_ops = {
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};
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const struct spinand_manufacturer foresee_spinand_manufacturer = {
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.id = SPINAND_MFR_FORESEE,
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.name = "FORESEE",
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.chips = foresee_spinand_table,
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.nchips = ARRAY_SIZE(foresee_spinand_table),
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.ops = &foresee_spinand_manuf_ops,
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};
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