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ac3a4b17e0
SPI operations have been initially described through macros implicitly implying the use of a single SPI SDR bus. Macros for supporting dual and quad I/O transfers have been added on top, generally inspired by vendor naming, followed by DTR operations. Soon we might see octal and even octal DTR operations as well (including the opcode byte). Let's clarify what the macro really means by describing the expected bus topology in the (quad) program load macro name. While at modifying it, better add the missing_ OP suffix to align with all the other macros of the same kind. Acked-by: Tudor Ambarus <tudor.ambarus@linaro.org> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
148 lines
4.6 KiB
C
148 lines
4.6 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2024 SkyHigh Memory Limited
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*
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* Author: Takahiro Kuwano <takahiro.kuwano@infineon.com>
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* Co-Author: KR Kim <kr.kim@skyhighmemory.com>
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*/
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#include <linux/device.h>
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#include <linux/kernel.h>
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#include <linux/mtd/spinand.h>
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#define SPINAND_MFR_SKYHIGH 0x01
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#define SKYHIGH_STATUS_ECC_1TO2_BITFLIPS (1 << 4)
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#define SKYHIGH_STATUS_ECC_3TO6_BITFLIPS (2 << 4)
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#define SKYHIGH_STATUS_ECC_UNCOR_ERROR (3 << 4)
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#define SKYHIGH_CONFIG_PROTECT_EN BIT(1)
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static SPINAND_OP_VARIANTS(read_cache_variants,
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SPINAND_PAGE_READ_FROM_CACHE_1S_4S_4S_OP(0, 4, NULL, 0),
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SPINAND_PAGE_READ_FROM_CACHE_1S_1S_4S_OP(0, 1, NULL, 0),
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SPINAND_PAGE_READ_FROM_CACHE_1S_2S_2S_OP(0, 2, NULL, 0),
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SPINAND_PAGE_READ_FROM_CACHE_1S_1S_2S_OP(0, 1, NULL, 0),
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SPINAND_PAGE_READ_FROM_CACHE_FAST_1S_1S_1S_OP(0, 1, NULL, 0),
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SPINAND_PAGE_READ_FROM_CACHE_1S_1S_1S_OP(0, 1, NULL, 0));
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static SPINAND_OP_VARIANTS(write_cache_variants,
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SPINAND_PROG_LOAD_1S_1S_4S_OP(true, 0, NULL, 0),
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SPINAND_PROG_LOAD_1S_1S_1S_OP(true, 0, NULL, 0));
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static SPINAND_OP_VARIANTS(update_cache_variants,
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SPINAND_PROG_LOAD_1S_1S_4S_OP(false, 0, NULL, 0),
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SPINAND_PROG_LOAD_1S_1S_1S_OP(false, 0, NULL, 0));
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static int skyhigh_spinand_ooblayout_ecc(struct mtd_info *mtd, int section,
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struct mtd_oob_region *region)
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{
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/* ECC bytes are stored in hidden area. */
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return -ERANGE;
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}
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static int skyhigh_spinand_ooblayout_free(struct mtd_info *mtd, int section,
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struct mtd_oob_region *region)
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{
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if (section)
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return -ERANGE;
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/* ECC bytes are stored in hidden area. Reserve 2 bytes for the BBM. */
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region->offset = 2;
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region->length = mtd->oobsize - 2;
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return 0;
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}
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static const struct mtd_ooblayout_ops skyhigh_spinand_ooblayout = {
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.ecc = skyhigh_spinand_ooblayout_ecc,
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.free = skyhigh_spinand_ooblayout_free,
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};
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static int skyhigh_spinand_ecc_get_status(struct spinand_device *spinand,
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u8 status)
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{
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switch (status & STATUS_ECC_MASK) {
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case STATUS_ECC_NO_BITFLIPS:
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return 0;
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case SKYHIGH_STATUS_ECC_UNCOR_ERROR:
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return -EBADMSG;
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case SKYHIGH_STATUS_ECC_1TO2_BITFLIPS:
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return 2;
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case SKYHIGH_STATUS_ECC_3TO6_BITFLIPS:
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return 6;
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default:
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break;
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}
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return -EINVAL;
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}
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static const struct spinand_info skyhigh_spinand_table[] = {
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SPINAND_INFO("S35ML01G301",
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SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x15),
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NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1),
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NAND_ECCREQ(6, 32),
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SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
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&write_cache_variants,
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&update_cache_variants),
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SPINAND_NO_RAW_ACCESS,
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SPINAND_ECCINFO(&skyhigh_spinand_ooblayout,
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skyhigh_spinand_ecc_get_status)),
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SPINAND_INFO("S35ML01G300",
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SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x14),
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NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1),
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NAND_ECCREQ(6, 32),
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SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
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&write_cache_variants,
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&update_cache_variants),
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SPINAND_NO_RAW_ACCESS,
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SPINAND_ECCINFO(&skyhigh_spinand_ooblayout,
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skyhigh_spinand_ecc_get_status)),
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SPINAND_INFO("S35ML02G300",
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SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x25),
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NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 2, 1, 1),
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NAND_ECCREQ(6, 32),
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SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
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&write_cache_variants,
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&update_cache_variants),
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SPINAND_NO_RAW_ACCESS,
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SPINAND_ECCINFO(&skyhigh_spinand_ooblayout,
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skyhigh_spinand_ecc_get_status)),
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SPINAND_INFO("S35ML04G300",
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SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x35),
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NAND_MEMORG(1, 2048, 128, 64, 4096, 80, 2, 1, 1),
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NAND_ECCREQ(6, 32),
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SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
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&write_cache_variants,
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&update_cache_variants),
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SPINAND_NO_RAW_ACCESS,
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SPINAND_ECCINFO(&skyhigh_spinand_ooblayout,
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skyhigh_spinand_ecc_get_status)),
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};
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static int skyhigh_spinand_init(struct spinand_device *spinand)
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{
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/*
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* Config_Protect_En (bit 1 in Block Lock register) must be set to 1
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* before writing other bits. Do it here before core unlocks all blocks
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* by writing block protection bits.
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*/
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return spinand_write_reg_op(spinand, REG_BLOCK_LOCK,
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SKYHIGH_CONFIG_PROTECT_EN);
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}
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static const struct spinand_manufacturer_ops skyhigh_spinand_manuf_ops = {
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.init = skyhigh_spinand_init,
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};
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const struct spinand_manufacturer skyhigh_spinand_manufacturer = {
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.id = SPINAND_MFR_SKYHIGH,
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.name = "SkyHigh",
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.chips = skyhigh_spinand_table,
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.nchips = ARRAY_SIZE(skyhigh_spinand_table),
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.ops = &skyhigh_spinand_manuf_ops,
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};
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