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This patch adds support for XDP_TX and XDP_REDIRECT for the DQ RDA queue format. To appropriately support transmission of XDP frames, a new pending packet type GVE_TX_PENDING_PACKET_DQO_XDP_FRAME is introduced for completion handling, as there was a previous assumption that completed packets would be SKBs. XDP_TX handling completes the basic XDP actions, so the feature is recorded accordingly. This patch also enables the ndo_xdp_xmit callback allowing DQ to handle XDP_REDIRECT packets originating from another interface. The XDP spinlock is moved to common TX ring fields so that it can be used in both GQ and DQ. Originally, it was in a section which was mutually exclusive for GQ and DQ. In summary, 3 XDP features are exposed for the DQ RDA queue format: 1) NETDEV_XDP_ACT_BASIC 2) NETDEV_XDP_ACT_NDO_XMIT 3) NETDEV_XDP_ACT_REDIRECT Note that XDP and header-data split are mutually exclusive for the time being due to lack of multi-buffer XDP support. This patch does not add support for the DQ QPL format. That is to come in a future patch series. Reviewed-by: Willem de Bruijn <willemb@google.com> Signed-off-by: Praveen Kaligineedi <pkaligineedi@google.com> Signed-off-by: Joshua Washington <joshwash@google.com> Signed-off-by: Harshitha Ramamurthy <hramamurthy@google.com> Signed-off-by: David S. Miller <davem@davemloft.net>
115 lines
3.7 KiB
C
115 lines
3.7 KiB
C
/* SPDX-License-Identifier: (GPL-2.0 OR MIT)
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* Google virtual Ethernet (gve) driver
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*
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* Copyright (C) 2015-2021 Google, Inc.
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*/
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#ifndef _GVE_DQO_H_
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#define _GVE_DQO_H_
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#include "gve_adminq.h"
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#define GVE_ITR_ENABLE_BIT_DQO BIT(0)
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#define GVE_ITR_CLEAR_PBA_BIT_DQO BIT(1)
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#define GVE_ITR_NO_UPDATE_DQO (3 << 3)
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#define GVE_ITR_INTERVAL_DQO_SHIFT 5
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#define GVE_ITR_INTERVAL_DQO_MASK ((1 << 12) - 1)
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#define GVE_TX_IRQ_RATELIMIT_US_DQO 50
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#define GVE_RX_IRQ_RATELIMIT_US_DQO 20
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#define GVE_MAX_ITR_INTERVAL_DQO (GVE_ITR_INTERVAL_DQO_MASK * 2)
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/* Timeout in seconds to wait for a reinjection completion after receiving
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* its corresponding miss completion.
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*/
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#define GVE_REINJECT_COMPL_TIMEOUT 1
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/* Timeout in seconds to deallocate the completion tag for a packet that was
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* prematurely freed for not receiving a valid completion. This should be large
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* enough to rule out the possibility of receiving the corresponding valid
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* completion after this interval.
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*/
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#define GVE_DEALLOCATE_COMPL_TIMEOUT 60
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netdev_tx_t gve_tx_dqo(struct sk_buff *skb, struct net_device *dev);
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netdev_features_t gve_features_check_dqo(struct sk_buff *skb,
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struct net_device *dev,
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netdev_features_t features);
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bool gve_tx_poll_dqo(struct gve_notify_block *block, bool do_clean);
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bool gve_xdp_poll_dqo(struct gve_notify_block *block);
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int gve_rx_poll_dqo(struct gve_notify_block *block, int budget);
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int gve_tx_alloc_rings_dqo(struct gve_priv *priv,
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struct gve_tx_alloc_rings_cfg *cfg);
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void gve_tx_free_rings_dqo(struct gve_priv *priv,
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struct gve_tx_alloc_rings_cfg *cfg);
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void gve_tx_start_ring_dqo(struct gve_priv *priv, int idx);
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void gve_tx_stop_ring_dqo(struct gve_priv *priv, int idx);
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int gve_rx_alloc_ring_dqo(struct gve_priv *priv,
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struct gve_rx_alloc_rings_cfg *cfg,
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struct gve_rx_ring *rx,
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int idx);
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void gve_rx_free_ring_dqo(struct gve_priv *priv, struct gve_rx_ring *rx,
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struct gve_rx_alloc_rings_cfg *cfg);
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int gve_rx_alloc_rings_dqo(struct gve_priv *priv,
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struct gve_rx_alloc_rings_cfg *cfg);
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void gve_rx_free_rings_dqo(struct gve_priv *priv,
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struct gve_rx_alloc_rings_cfg *cfg);
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void gve_rx_start_ring_dqo(struct gve_priv *priv, int idx);
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void gve_rx_stop_ring_dqo(struct gve_priv *priv, int idx);
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int gve_clean_tx_done_dqo(struct gve_priv *priv, struct gve_tx_ring *tx,
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struct napi_struct *napi);
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void gve_rx_post_buffers_dqo(struct gve_rx_ring *rx);
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void gve_rx_write_doorbell_dqo(const struct gve_priv *priv, int queue_idx);
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void gve_xdp_tx_flush_dqo(struct gve_priv *priv, u32 xdp_qid);
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static inline void
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gve_tx_put_doorbell_dqo(const struct gve_priv *priv,
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const struct gve_queue_resources *q_resources, u32 val)
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{
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u64 index;
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index = be32_to_cpu(q_resources->db_index);
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iowrite32(val, &priv->db_bar2[index]);
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}
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/* Builds register value to write to DQO IRQ doorbell to enable with specified
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* ITR interval.
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*/
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static inline u32 gve_setup_itr_interval_dqo(u32 interval_us)
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{
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u32 result = GVE_ITR_ENABLE_BIT_DQO;
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/* Interval has 2us granularity. */
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interval_us >>= 1;
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interval_us &= GVE_ITR_INTERVAL_DQO_MASK;
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result |= (interval_us << GVE_ITR_INTERVAL_DQO_SHIFT);
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return result;
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}
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static inline void
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gve_write_irq_doorbell_dqo(const struct gve_priv *priv,
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const struct gve_notify_block *block, u32 val)
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{
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u32 index = be32_to_cpu(*block->irq_db_index);
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iowrite32(val, &priv->db_bar2[index]);
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}
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/* Sets interrupt throttling interval and enables interrupt
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* by writing to IRQ doorbell.
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*/
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static inline void
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gve_set_itr_coalesce_usecs_dqo(struct gve_priv *priv,
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struct gve_notify_block *block,
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u32 usecs)
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{
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gve_write_irq_doorbell_dqo(priv, block,
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gve_setup_itr_interval_dqo(usecs));
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}
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int gve_napi_poll_dqo(struct napi_struct *napi, int budget);
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#endif /* _GVE_DQO_H_ */
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