mirror of
https://github.com/raspberrypi/linux.git
synced 2025-12-24 11:02:51 +00:00
e5075d8ec5
Pull more RISC-V updates from Palmer Dabbelt: - Support for tuning for systems with fast misaligned accesses. - Support for SBI-based suspend. - Support for the new SBI debug console extension. - The T-Head CMOs now use PA-based flushes. - Support for enabling the V extension in kernel code. - Optimized IP checksum routines. - Various ftrace improvements. - Support for archrandom, which depends on the Zkr extension. - The build is no longer broken under NET=n, KUNIT=y for ports that don't define their own ipv6 checksum. * tag 'riscv-for-linus-6.8-mw4' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux: (56 commits) lib: checksum: Fix build with CONFIG_NET=n riscv: lib: Check if output in asm goto supported riscv: Fix build error on rv32 + XIP riscv: optimize ELF relocation function in riscv RISC-V: Implement archrandom when Zkr is available riscv: Optimize hweight API with Zbb extension riscv: add dependency among Image(.gz), loader(.bin), and vmlinuz.efi samples: ftrace: Add RISC-V support for SAMPLE_FTRACE_DIRECT[_MULTI] riscv: ftrace: Add DYNAMIC_FTRACE_WITH_DIRECT_CALLS support riscv: ftrace: Make function graph use ftrace directly riscv: select FTRACE_MCOUNT_USE_PATCHABLE_FUNCTION_ENTRY lib/Kconfig.debug: Update AS_HAS_NON_CONST_LEB128 comment and name riscv: Restrict DWARF5 when building with LLVM to known working versions riscv: Hoist linker relaxation disabling logic into Kconfig kunit: Add tests for csum_ipv6_magic and ip_fast_csum riscv: Add checksum library riscv: Add checksum header riscv: Add static key for misaligned accesses asm-generic: Improve csum_fold RISC-V: selftests: cbo: Ensure asm operands match constraints ...
84 lines
1.7 KiB
C
84 lines
1.7 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2008 David Gibson, IBM Corporation
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* Copyright (C) 2012 Regents of the University of California
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* Copyright (C) 2017 SiFive
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*/
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#include <linux/console.h>
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#include <linux/err.h>
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#include <linux/init.h>
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#include <linux/moduleparam.h>
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#include <linux/types.h>
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#include <asm/sbi.h>
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#include "hvc_console.h"
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static ssize_t hvc_sbi_tty_put(uint32_t vtermno, const u8 *buf, size_t count)
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{
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size_t i;
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for (i = 0; i < count; i++)
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sbi_console_putchar(buf[i]);
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return i;
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}
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static ssize_t hvc_sbi_tty_get(uint32_t vtermno, u8 *buf, size_t count)
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{
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size_t i;
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int c;
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for (i = 0; i < count; i++) {
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c = sbi_console_getchar();
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if (c < 0)
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break;
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buf[i] = c;
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}
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return i;
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}
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static const struct hv_ops hvc_sbi_v01_ops = {
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.get_chars = hvc_sbi_tty_get,
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.put_chars = hvc_sbi_tty_put,
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};
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static ssize_t hvc_sbi_dbcn_tty_put(uint32_t vtermno, const u8 *buf, size_t count)
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{
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return sbi_debug_console_write(buf, count);
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}
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static ssize_t hvc_sbi_dbcn_tty_get(uint32_t vtermno, u8 *buf, size_t count)
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{
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return sbi_debug_console_read(buf, count);
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}
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static const struct hv_ops hvc_sbi_dbcn_ops = {
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.put_chars = hvc_sbi_dbcn_tty_put,
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.get_chars = hvc_sbi_dbcn_tty_get,
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};
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static int __init hvc_sbi_init(void)
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{
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int err;
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if (sbi_debug_console_available) {
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err = PTR_ERR_OR_ZERO(hvc_alloc(0, 0, &hvc_sbi_dbcn_ops, 256));
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if (err)
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return err;
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hvc_instantiate(0, 0, &hvc_sbi_dbcn_ops);
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} else if (IS_ENABLED(CONFIG_RISCV_SBI_V01)) {
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err = PTR_ERR_OR_ZERO(hvc_alloc(0, 0, &hvc_sbi_v01_ops, 256));
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if (err)
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return err;
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hvc_instantiate(0, 0, &hvc_sbi_v01_ops);
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} else {
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return -ENODEV;
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}
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return 0;
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}
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device_initcall(hvc_sbi_init);
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