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https://github.com/raspberrypi/linux.git
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97d8894b6f
Pull RISC-V updates from Palmer Dabbelt: - Support using Zkr to seed KASLR - Support IPI-triggered CPU backtracing - Support for generic CPU vulnerabilities reporting to userspace - A few cleanups for missing licenses - The size limit on the XIP kernel has been removed - Support for tracing userspace stacks - Support for the Svvptc extension - Various cleanups and fixes throughout the tree * tag 'riscv-for-linus-6.12-mw1' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux: (47 commits) crash: Fix riscv64 crash memory reserve dead loop perf/riscv-sbi: Add platform specific firmware event handling tools: Optimize ring buffer for riscv tools: Add riscv barrier implementation RISC-V: Don't have MAX_PHYSMEM_BITS exceed phys_addr_t ACPI: NUMA: initialize all values of acpi_early_node_map to NUMA_NO_NODE riscv: Enable bitops instrumentation riscv: Omit optimized string routines when using KASAN ACPI: RISCV: Make acpi_numa_get_nid() to be static riscv: Randomize lower bits of stack address selftests: riscv: Allow mmap test to compile on 32-bit riscv: Make riscv_isa_vendor_ext_andes array static riscv: Use LIST_HEAD() to simplify code riscv: defconfig: Disable RZ/Five peripheral support RISC-V: Implement kgdb_roundup_cpus() to enable future NMI Roundup riscv: avoid Imbalance in RAS riscv: cacheinfo: Add back init_cache_level() function riscv: Remove unused _TIF_WORK_MASK drivers/perf: riscv: Remove redundant macro check riscv: define ILLEGAL_POINTER_VALUE for 64bit ...
80 lines
2.1 KiB
C
80 lines
2.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (C) 2012 Regents of the University of California
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* Copyright (C) 2017 SiFive
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*/
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#ifndef _ASM_RISCV_IRQ_H
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#define _ASM_RISCV_IRQ_H
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#include <linux/interrupt.h>
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#include <linux/linkage.h>
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#include <asm-generic/irq.h>
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#define INVALID_CONTEXT UINT_MAX
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#ifdef CONFIG_SMP
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void arch_trigger_cpumask_backtrace(const cpumask_t *mask, int exclude_cpu);
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#define arch_trigger_cpumask_backtrace arch_trigger_cpumask_backtrace
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#endif
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void riscv_set_intc_hwnode_fn(struct fwnode_handle *(*fn)(void));
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struct fwnode_handle *riscv_get_intc_hwnode(void);
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#ifdef CONFIG_ACPI
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enum riscv_irqchip_type {
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ACPI_RISCV_IRQCHIP_INTC = 0x00,
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ACPI_RISCV_IRQCHIP_IMSIC = 0x01,
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ACPI_RISCV_IRQCHIP_PLIC = 0x02,
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ACPI_RISCV_IRQCHIP_APLIC = 0x03,
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};
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int riscv_acpi_get_gsi_info(struct fwnode_handle *fwnode, u32 *gsi_base,
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u32 *id, u32 *nr_irqs, u32 *nr_idcs);
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struct fwnode_handle *riscv_acpi_get_gsi_domain_id(u32 gsi);
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unsigned long acpi_rintc_index_to_hartid(u32 index);
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unsigned long acpi_rintc_ext_parent_to_hartid(unsigned int plic_id, unsigned int ctxt_idx);
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unsigned int acpi_rintc_get_plic_nr_contexts(unsigned int plic_id);
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unsigned int acpi_rintc_get_plic_context(unsigned int plic_id, unsigned int ctxt_idx);
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int __init acpi_rintc_get_imsic_mmio_info(u32 index, struct resource *res);
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#else
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static inline int riscv_acpi_get_gsi_info(struct fwnode_handle *fwnode, u32 *gsi_base,
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u32 *id, u32 *nr_irqs, u32 *nr_idcs)
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{
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return 0;
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}
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static inline unsigned long acpi_rintc_index_to_hartid(u32 index)
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{
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return INVALID_HARTID;
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}
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static inline unsigned long acpi_rintc_ext_parent_to_hartid(unsigned int plic_id,
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unsigned int ctxt_idx)
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{
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return INVALID_HARTID;
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}
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static inline unsigned int acpi_rintc_get_plic_nr_contexts(unsigned int plic_id)
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{
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return INVALID_CONTEXT;
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}
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static inline unsigned int acpi_rintc_get_plic_context(unsigned int plic_id, unsigned int ctxt_idx)
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{
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return INVALID_CONTEXT;
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}
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static inline int __init acpi_rintc_get_imsic_mmio_info(u32 index, struct resource *res)
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{
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return 0;
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}
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#endif /* CONFIG_ACPI */
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#endif /* _ASM_RISCV_IRQ_H */
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