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W25N01JW and W25N02JW support many DTR read modes in single, dual and quad configurations. DTR modes however cannot be used at 166MHz, as the bus frequency in this case must be lowered to 80MHz. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
318 lines
9.8 KiB
C
318 lines
9.8 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2017 exceet electronics GmbH
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*
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* Authors:
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* Frieder Schrempf <frieder.schrempf@exceet.de>
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* Boris Brezillon <boris.brezillon@bootlin.com>
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*/
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#include <linux/device.h>
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#include <linux/kernel.h>
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#include <linux/mtd/spinand.h>
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#include <linux/units.h>
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#define SPINAND_MFR_WINBOND 0xEF
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#define WINBOND_CFG_BUF_READ BIT(3)
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#define W25N04KV_STATUS_ECC_5_8_BITFLIPS (3 << 4)
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/*
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* "X2" in the core is equivalent to "dual output" in the datasheets,
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* "X4" in the core is equivalent to "quad output" in the datasheets.
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*/
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static SPINAND_OP_VARIANTS(read_cache_dtr_variants,
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SPINAND_PAGE_READ_FROM_CACHE_QUADIO_DTR_OP(0, 8, NULL, 0, 80 * HZ_PER_MHZ),
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SPINAND_PAGE_READ_FROM_CACHE_X4_DTR_OP(0, 2, NULL, 0, 80 * HZ_PER_MHZ),
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SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 2, NULL, 0),
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SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0),
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SPINAND_PAGE_READ_FROM_CACHE_DUALIO_DTR_OP(0, 4, NULL, 0, 80 * HZ_PER_MHZ),
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SPINAND_PAGE_READ_FROM_CACHE_X2_DTR_OP(0, 2, NULL, 0, 80 * HZ_PER_MHZ),
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SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP(0, 1, NULL, 0),
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SPINAND_PAGE_READ_FROM_CACHE_X2_OP(0, 1, NULL, 0),
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SPINAND_PAGE_READ_FROM_CACHE_DTR_OP(0, 2, NULL, 0, 80 * HZ_PER_MHZ),
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SPINAND_PAGE_READ_FROM_CACHE_FAST_OP(0, 1, NULL, 0),
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SPINAND_PAGE_READ_FROM_CACHE_OP(0, 1, NULL, 0, 54 * HZ_PER_MHZ));
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static SPINAND_OP_VARIANTS(read_cache_variants,
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SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 2, NULL, 0),
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SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0),
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SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP(0, 1, NULL, 0),
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SPINAND_PAGE_READ_FROM_CACHE_X2_OP(0, 1, NULL, 0),
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SPINAND_PAGE_READ_FROM_CACHE_FAST_OP(0, 1, NULL, 0),
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SPINAND_PAGE_READ_FROM_CACHE_OP(0, 1, NULL, 0));
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static SPINAND_OP_VARIANTS(write_cache_variants,
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SPINAND_PROG_LOAD_X4(true, 0, NULL, 0),
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SPINAND_PROG_LOAD(true, 0, NULL, 0));
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static SPINAND_OP_VARIANTS(update_cache_variants,
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SPINAND_PROG_LOAD_X4(false, 0, NULL, 0),
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SPINAND_PROG_LOAD(false, 0, NULL, 0));
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static int w25m02gv_ooblayout_ecc(struct mtd_info *mtd, int section,
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struct mtd_oob_region *region)
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{
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if (section > 3)
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return -ERANGE;
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region->offset = (16 * section) + 8;
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region->length = 8;
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return 0;
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}
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static int w25m02gv_ooblayout_free(struct mtd_info *mtd, int section,
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struct mtd_oob_region *region)
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{
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if (section > 3)
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return -ERANGE;
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region->offset = (16 * section) + 2;
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region->length = 6;
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return 0;
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}
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static const struct mtd_ooblayout_ops w25m02gv_ooblayout = {
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.ecc = w25m02gv_ooblayout_ecc,
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.free = w25m02gv_ooblayout_free,
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};
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static int w25m02gv_select_target(struct spinand_device *spinand,
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unsigned int target)
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{
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struct spi_mem_op op = SPI_MEM_OP(SPI_MEM_OP_CMD(0xc2, 1),
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SPI_MEM_OP_NO_ADDR,
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SPI_MEM_OP_NO_DUMMY,
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SPI_MEM_OP_DATA_OUT(1,
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spinand->scratchbuf,
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1));
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*spinand->scratchbuf = target;
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return spi_mem_exec_op(spinand->spimem, &op);
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}
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static int w25n01kv_ooblayout_ecc(struct mtd_info *mtd, int section,
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struct mtd_oob_region *region)
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{
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if (section > 3)
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return -ERANGE;
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region->offset = 64 + (8 * section);
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region->length = 7;
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return 0;
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}
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static int w25n02kv_ooblayout_ecc(struct mtd_info *mtd, int section,
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struct mtd_oob_region *region)
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{
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if (section > 3)
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return -ERANGE;
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region->offset = 64 + (16 * section);
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region->length = 13;
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return 0;
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}
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static int w25n02kv_ooblayout_free(struct mtd_info *mtd, int section,
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struct mtd_oob_region *region)
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{
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if (section > 3)
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return -ERANGE;
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region->offset = (16 * section) + 2;
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region->length = 14;
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return 0;
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}
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static const struct mtd_ooblayout_ops w25n01kv_ooblayout = {
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.ecc = w25n01kv_ooblayout_ecc,
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.free = w25n02kv_ooblayout_free,
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};
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static const struct mtd_ooblayout_ops w25n02kv_ooblayout = {
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.ecc = w25n02kv_ooblayout_ecc,
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.free = w25n02kv_ooblayout_free,
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};
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static int w25n02kv_ecc_get_status(struct spinand_device *spinand,
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u8 status)
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{
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struct nand_device *nand = spinand_to_nand(spinand);
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u8 mbf = 0;
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struct spi_mem_op op = SPINAND_GET_FEATURE_OP(0x30, spinand->scratchbuf);
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switch (status & STATUS_ECC_MASK) {
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case STATUS_ECC_NO_BITFLIPS:
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return 0;
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case STATUS_ECC_UNCOR_ERROR:
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return -EBADMSG;
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case STATUS_ECC_HAS_BITFLIPS:
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case W25N04KV_STATUS_ECC_5_8_BITFLIPS:
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/*
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* Let's try to retrieve the real maximum number of bitflips
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* in order to avoid forcing the wear-leveling layer to move
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* data around if it's not necessary.
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*/
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if (spi_mem_exec_op(spinand->spimem, &op))
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return nanddev_get_ecc_conf(nand)->strength;
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mbf = *(spinand->scratchbuf) >> 4;
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if (WARN_ON(mbf > nanddev_get_ecc_conf(nand)->strength || !mbf))
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return nanddev_get_ecc_conf(nand)->strength;
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return mbf;
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default:
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break;
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}
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return -EINVAL;
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}
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static const struct spinand_info winbond_spinand_table[] = {
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/* 512M-bit densities */
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SPINAND_INFO("W25N512GW", /* 1.8V */
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SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xba, 0x20),
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NAND_MEMORG(1, 2048, 64, 64, 512, 10, 1, 1, 1),
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NAND_ECCREQ(1, 512),
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SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
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&write_cache_variants,
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&update_cache_variants),
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0,
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SPINAND_ECCINFO(&w25m02gv_ooblayout, NULL)),
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/* 1G-bit densities */
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SPINAND_INFO("W25N01GV", /* 3.3V */
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SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xaa, 0x21),
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NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1),
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NAND_ECCREQ(1, 512),
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SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
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&write_cache_variants,
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&update_cache_variants),
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0,
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SPINAND_ECCINFO(&w25m02gv_ooblayout, NULL)),
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SPINAND_INFO("W25N01GW", /* 1.8V */
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SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xba, 0x21),
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NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1),
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NAND_ECCREQ(1, 512),
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SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
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&write_cache_variants,
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&update_cache_variants),
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0,
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SPINAND_ECCINFO(&w25m02gv_ooblayout, NULL)),
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SPINAND_INFO("W25N01JW", /* high-speed 1.8V */
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SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xbc, 0x21),
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NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1),
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NAND_ECCREQ(1, 512),
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SPINAND_INFO_OP_VARIANTS(&read_cache_dtr_variants,
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&write_cache_variants,
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&update_cache_variants),
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0,
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SPINAND_ECCINFO(&w25m02gv_ooblayout, NULL)),
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SPINAND_INFO("W25N01KV", /* 3.3V */
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SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xae, 0x21),
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NAND_MEMORG(1, 2048, 96, 64, 1024, 20, 1, 1, 1),
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NAND_ECCREQ(4, 512),
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SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
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&write_cache_variants,
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&update_cache_variants),
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0,
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SPINAND_ECCINFO(&w25n01kv_ooblayout, w25n02kv_ecc_get_status)),
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/* 2G-bit densities */
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SPINAND_INFO("W25M02GV", /* 2x1G-bit 3.3V */
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SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xab, 0x21),
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NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 2),
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NAND_ECCREQ(1, 512),
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SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
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&write_cache_variants,
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&update_cache_variants),
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0,
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SPINAND_ECCINFO(&w25m02gv_ooblayout, NULL),
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SPINAND_SELECT_TARGET(w25m02gv_select_target)),
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SPINAND_INFO("W25N02JW", /* high-speed 1.8V */
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SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xbf, 0x22),
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NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 2, 1),
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NAND_ECCREQ(1, 512),
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SPINAND_INFO_OP_VARIANTS(&read_cache_dtr_variants,
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&write_cache_variants,
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&update_cache_variants),
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0,
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SPINAND_ECCINFO(&w25m02gv_ooblayout, NULL)),
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SPINAND_INFO("W25N02KV", /* 3.3V */
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SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xaa, 0x22),
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NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1),
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NAND_ECCREQ(8, 512),
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SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
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&write_cache_variants,
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&update_cache_variants),
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0,
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SPINAND_ECCINFO(&w25n02kv_ooblayout, w25n02kv_ecc_get_status)),
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SPINAND_INFO("W25N02KW", /* 1.8V */
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SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xba, 0x22),
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NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1),
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NAND_ECCREQ(8, 512),
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SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
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&write_cache_variants,
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&update_cache_variants),
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0,
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SPINAND_ECCINFO(&w25n02kv_ooblayout, w25n02kv_ecc_get_status)),
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/* 4G-bit densities */
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SPINAND_INFO("W25N04KV", /* 3.3V */
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SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xaa, 0x23),
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NAND_MEMORG(1, 2048, 128, 64, 4096, 40, 2, 1, 1),
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NAND_ECCREQ(8, 512),
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SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
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&write_cache_variants,
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&update_cache_variants),
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0,
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SPINAND_ECCINFO(&w25n02kv_ooblayout, w25n02kv_ecc_get_status)),
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SPINAND_INFO("W25N04KW", /* 1.8V */
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SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xba, 0x23),
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NAND_MEMORG(1, 2048, 128, 64, 4096, 40, 1, 1, 1),
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NAND_ECCREQ(8, 512),
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SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
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&write_cache_variants,
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&update_cache_variants),
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0,
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SPINAND_ECCINFO(&w25n02kv_ooblayout, w25n02kv_ecc_get_status)),
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};
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static int winbond_spinand_init(struct spinand_device *spinand)
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{
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struct nand_device *nand = spinand_to_nand(spinand);
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unsigned int i;
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/*
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* Make sure all dies are in buffer read mode and not continuous read
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* mode.
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*/
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for (i = 0; i < nand->memorg.ntargets; i++) {
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spinand_select_target(spinand, i);
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spinand_upd_cfg(spinand, WINBOND_CFG_BUF_READ,
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WINBOND_CFG_BUF_READ);
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}
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return 0;
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}
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static const struct spinand_manufacturer_ops winbond_spinand_manuf_ops = {
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.init = winbond_spinand_init,
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};
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const struct spinand_manufacturer winbond_spinand_manufacturer = {
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.id = SPINAND_MFR_WINBOND,
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.name = "Winbond",
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.chips = winbond_spinand_table,
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.nchips = ARRAY_SIZE(winbond_spinand_table),
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.ops = &winbond_spinand_manuf_ops,
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};
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