Martin Leung 90f33674a0 drm/amd/display: Prepare for new interfaces ...

[WHY]:
Lut pipeline will be hooked up differently in some asics
need to add new interfaces and missing registers.

[HOW]:
Add missing registers and hook up programming from DPP for pre-blend
lut.

Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Martin Leung <Martin.Leung@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

2022-07-05 16:10:45 -04:00

..

amdgpu_dm

drm/amd: Add debug mask for subviewport mclk switch

2022-07-05 16:09:24 -04:00

dc

drm/amd/display: Prepare for new interfaces

2022-07-05 16:10:45 -04:00

dmub

drm/amd/display: Add SubVP required code

2022-07-05 16:10:38 -04:00

include

drm/amd/display: rename lane_settings to hw_lane_settings

2022-06-21 18:17:23 -04:00

modules

drm/amd/display: Add vrr_active_variable to dc_stream_update

2022-06-14 21:38:41 -04:00

Kconfig

drm/display: Move HDCP helpers into display-helper module

2022-04-25 11:19:36 +02:00

Makefile

drm/amd/display: Drop CONFIG_DRM_AMD_DC_DMUB guards

2019-11-13 15:29:42 -05:00

TODO

drm/amd/display: Convert remaining loggers off dc_logger

2018-07-13 14:48:42 -05:00